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  1. Digital Systems II: Intro Beginnings J. Schmalzel R. Polikar

  2. CPU MEM I/O Digital Foundations • The basic model of a computer system:

  3. Central Processing Unit (CPU) • Controls • Executes • Computes (Fixed- and/or Floating-Point)

  4. Memory • Program store • Data storage • High-speedLow-speed • Volatile, Non-volatile • RAM, ROM, FLASH (EEPROM) • FastSlow

  5. Input/Output (I/O) • Communication between CPU and outside world • FastSlow • Standardized (e.g., IEEE 802.11b) • Parallel (IEEE 1184)Serial (USB 2.0)

  6. CPU MEM I/O Hierarchical View of EP and Digital Systems Operating System HLLs Computer Architecture State Machines Interface Method Design Techniques MSI Functions Boolean Algebra Gates

  7. Sequential Circuits • Include feedback • Presence of a clock • Behavior is no longer simply a function of the inputs--must be evaluated synchronously with clock • Flip-flops • D-type • J-K type • etc.

  8. P C Dn Qn+1 0 1 X 1 1 0 X 0 0 0 X Illegal 0 1 1 0 1 1 1 1 D-F/F P D Q CK Q* Excitation Function: Dn = Qn+1 C

  9. Xilinx F/F’s FDC: D-F/F w/ asynchronous clear FDS: D-F/F w/ synchronous set The FDS will not set upon activation of the set input without also activating clock

  10. State Machines • Mealy: Outputs depend on states and on inputs. • Moore: Outputs depend only on states. • One-Hot: A type of Moore machine in which there is one F/F per state.

  11. State Machine Models State Memory Moore Outputs (& One-Hot) Clk Mealy Outputs Inputs Combinatorial Network

  12. Sequential Circuit Design • Problem statement • State diagram • Transition table • Simplified excitation functions • Implementation • Verification

  13. SM Z 1011 Example Design a sequence detector that will identify 1011.

  14. State Diagram Input/Output Input Name Output Name Input/Output Input Moore Mealy

  15. One-Hot SMs • Moore machines are glitchless since outputs change only synchronously with clock. • For relatively small numbers of states, techniques of F/F minimization are largely counterproductive with available “sea-of-gates” FPGA. • A 12-state SM: Don’t bother to reduce/encode. • A 16-bit counter: Definitely encode states.

  16. SM for 1011 Sequence Detector 0 Reset 1 1 Found None Found1 0 1 0 Found4 Z Found2 0 1 0 1 Found3 Note: Dashed lines show non-resetting algorithm.

  17. Transition Table Output Present State Input Next State Z F0 F1 F2 F3 F4 X F0’ F1’ F2’ F3’ F4’ 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0

  18. Excitation Functions The Transition Table could be large: 26 = 64, but since this is a One-Hot SM, there can be only one state active at a time. When writing the BA for each excitation function, listing the complemented states is redundant. For example: DF0 = F0•X* + F2•X*, instead of DF0 = F0•F1*•F2*•F3*•F4*•X* + F0*•F1*•F2•F3*•F4*• X* Similarly, DF1 = F0•X + F1•X + F4•X DF2 = F1•X* + F3•X* + F4•X* DF3 = F2•X DF4 = F3•X

  19. Simplification • If there are any redundant terms, can simplify; however, for One-Hot approach, there are no simplifications possible since must account for every separate state path.

  20. & + D Q & Implementation Assign one D-F/F per state and complete the combinatorial network required for each input. Implementation of F0 is shown: F0 X* P F0 F2 X* Clk The final network output, Z = F4. For reset, use asynchronous F/F inputs: Preset F0 and clear F1-F4.

  21. Verification • Check that the SM performs as required. • More complex input vectors are required since the internal state memory expands total possible states. • Use simulation tools.

  22. & + D Q & The Power of One-Hot Design • Can skip transition table--“read” the implementation directly off the state diagram: 1 1 Found None Found1 F0 X F1 F1 X C Clk

  23. Sequential Circuit Functions • Counters • Binary, BCD • Ripple, Synchronous • Registers and Latches • PIPO, PISO, SIPO, SISO

  24. In-Class Lab • Refer to EP Schematic 090-0016 • What is the function of U5? • Explain how it operates--what is the address of LED3? • How does it drive the LEDs? • What currents are supplied (in or out) by the 74HC259 to light up the LEDs?

  25. In-Class Lab • What is the function of U5? Addressable latch to control annunciators. • Explain how it operates--what is the address of LED3? An I/O write to address (CS1+2) enables the D-F/F, Q2. • How does it drive the LEDs? A logic 1 output forward-biases the LEDs, turning them on. The current-limiting resistors prevent excessive forward current. Assuming Vf of the LED is approx. 1.7 V, the current through the diode would be about (4.3-1.7)V/470 = 5.5 mA (which is nearly one of the specified load currents!). When an output is a logic 0, the associated LED is zero biased, which won’t turn it on. • What currents are supplied (in or out) by the 74HC259 to light up the LEDs?

  26. Digital v. Analog Electronics • Digital: Concerned with (usually) only two logic levels. Uses saturating logic circuits. For example, “1” = 5.0, “0” = 0.0 • Analog: Concerned with potentially infinite number of values between two extremes. For example, 0.0 < V < 5.0.

  27. In-Class Lab • ESD Principles • Brief tour of Z-World Core Module • Assembly notes • Software notes • Demo

  28. ESD Principles • Minimize electrostatic charge generation • Neutralize charges • Drain off charges • Minimize electrostatic fields and discharge effects • Protect ESD-sensitive devices during handling and transport Treat every device as if it were ESD sensitive!

  29. Electrical Model of ESD Field Equipment 1 M 1 M Snap (Wrist) Snap (Mat) Probe

  30. Assembly Notes • Objective is to add headers and other components to add test points and features. • Good construction practices. • Good soldering practices.

  31. CPU MEM I/O Introduction to Embedded Processors • Into the model of an embedded computer system:

  32. Introduction to Embedded Processors: User v. Developer • User • Transparent product/performance • Low-cost • Excellent interaction design • Developer • Meet schedule and budget (Reuse earlier S/W and H/W--finish project w/o forgoing sleep) • Meet marketing’s specifications • Do it better than the last time

  33. CPU MEM I/O Digital Foundations: The Architecture of an EP • The basic model of a computer system:

  34. CPU MEM I/O The Bus-Oriented EP Add Data Con

  35. Bus Basics Need to provide a shared medium that prevents contention. Use of these methods provides a way to provide bidirectional signal paths. Of course, does require arbitration. A Y Tri-State: “1” “0” and “High-Z” Open-Collector (Drain): Passively pulled high (“1”) or actively pulled low (“0”) E A E Y 0 1 0 1 1 1 X 0 Z

  36. Small footprint 25.8 MHz CPU 40 CMOS-compatible parallel I/O lines Four CMOS-compatible serial ports; max async rate of 806 kbps, max sync rate of 6.45 Mbps 8-bit data bus 13 address lines Control signals (I/O read, write) Master/slave config Reset input, output 5, 8-bit and 2, 10-bit timers 256K flash EPROM, 512KB SRAM RTC Status, WDT outputs Example EP Feature List

  37. Questions, Comments, Discussion