Automated synthesis of micro-pipelines from behavioral Verilog HDL

1. Automated synthesis of micro-pipelines from behavioral Verilog HDL Ivan Blunno Politecnico di Torino Luciano Lavagno Università di Udine

2. The target of our work HDL Specification Asynchronous Control Unit Synchronous Data Path

3. Motivation • Language-based design key enabler to synchronous logic success • Use HDL as single language for • specification • logic simulation and debugging • synthesis-layout generation • post-layout simulation • HDL must support multiple levels of abstraction

4. Control-data partitioning • Splitting of asynchronous control and synchronous data path • Automated insertion of bundling delays CONTROL UNIT request DATA PATH DATA delay acknowledge

5. Control-data partitioning • Splitting of asynchronous control and synchronous data path • Automated insertion of bundling delays CONTROL UNIT request DATA PATH CK DATA delay acknowledge

6. Control-data partitioning • Splitting of asynchronous control and synchronous data path • Automated insertion of bundling delays CONTROL UNIT request DATA PATH DATA delay ACK acknowledge

7. Synthesizable HDL specification Control/data splitting STG specification Logic delays Timing analysis (Synopsys) Logic implementation HDL netlist implementation Delay insertion D.P. synthesis Design flow Behavioral HDL specification C.U. synthesis Synthesis (Synopsys-DC) Synthesis (petrify)

8. HDL choice: standard HDL • several tools available, broad user basis • BUT syntax and semantics oriented to gates, (not STGs or BFSMs or process algebra) need to define a subset for synthesis Choice • VHDL • Verilog

9. Asynchronous Verilog subset • Declarations • Initialization and main loop • Asynchronous Verilog blocks • wait statements • Block assignments • if - else statements

10. Initialization and main loop • Module and signal declaration: • module example(a, b, c, d); • input a, b[7..0]; • output c, d; • reg e, f, g[11..0]; • Currently only single module synthesized • always loop surrounds live behavior • initial block defines initialization sequence

11. Asynchronous Verilog blocks Only structured mix of sequencing, concurrency and choice can be specified • begin-end for sequencing • fork-join for concurrency • if-else for input choice

12. .... start+ .... WAIT statement .... wait(start); .... STG

13. D.P. block diagram C.U. STG register - MUX Assignments RES = 0; ...... ...... RES = A + B; RES 0 A + B RES_out cmd_RES_0_out

14. D.P. Verilog specification always @(posedge RES_out) begin if(cmd_RES_0_out == 0) begin RES = 0; end if(cmd_RES_0_out == 1) begin RES = A + B; end end C.U. STG register - MUX Assignments RES = 0; ...... ...... RES = A + B;

15. Assignments: STG specification REG control load register req RES_out+ RES_in- RES_in+ load register ack RES_out- reg 4ph completion

16. D.P. block diagram C.U. STG register - MUX Assignments RES = 0; ...... ...... RES = A + B; RES 0 A + B RES_out cmd_RES_0_out

17. MUX control select mux req cmd_RES_0_out+ select mux ack cmd_RES_0_in+ cmd_RES_0_out- mux 4ph completion cmd_RES_0_in- Assignments: STG specification REG control load register req RES_out+ RES_in- RES_in+ load register ack RES_out- reg 4ph completion

18. C.U. STG IF - ELSE statements if(RES[7] == 1) ..... else ..... D.P. block diagram CMP FF 1 cmp_0 RES[7] cmd_cmp_0_out comparator - FF

19. C.U. STG IF - ELSE statements if(RES[7] == 1) ..... else ..... D.P. Verilog specification always @(posedge cmd_cmp_0_out) begin if(RES[7] == 1) cmp_0 = 1; else cmp_0 = 0; end comparator - FF

20. IF - ELSE statements: STG specification cmp_0- Pzero Pone cmp_0+ PH trF trT ELSE branch IF branch PK trQ

21. C.U. STG IF - ELSE statements if(RES[7] == 1) ..... else ..... D.P. block diagram CMP FF 1 cmp_0 RES[7] cmd_cmp_0_out comparator - FF

22. IF - ELSE statements: STG specification cmd_cmp_0_out+ cmd_cmp_0_in+ cmp_0- Pzero PF Pone cmp_0+ PH trF trT ELSE branch IF branch PK trQ

23. if(RES[7] == 1)

24. Example: FIR filter RES [z] = SMP [z] * 4 + SMP [z - 1] * 3 (saturating arithmetic) SMP * * SMP R R E S + RES RES start C.U. start done done

25. Example: FIR filter always begin wait(start); RES = SMP * 4 + R; R = SMP * 3; if(RES[7] == 1) RES = 0; else begin if(RES[6] == 1) RES = h3F; end; done = 1; wait(!start); done = 0; end SMP * * R R E S + RES C.U. start done

26. Final STG

27. Future work • Extension of Verilog HDL subset • Data Path and Control Unit optimizations • Module interface design automation. • Syntax-directed state encoding to speed up control unit logic synthesis