Verilog HDL -Introduction. VLSI Group –DAIICT Kishore, Aditya & Harsha. Ref: Verilog – HDL by samir palnitkar 2 nd Edition. Module- Basic building block. A module can be an element or collection of low level design blocks. Levels of Abstraction-1.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
VLSI Group –DAIICT
Kishore, Aditya & Harsha
Ref: Verilog – HDL by samir palnitkar 2nd Edition
A module can be an element or collection of low level design blocks
Rise Delay: Delay associated with a o/p transition to 1 from any value.
Fall Delay: Delay associated with o/p transition to 0 from any value.
Turn off Delay: Delay associate with o/p transition to Z from another value.