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2006 ITRS Public Conference Emerging Research Devices Hsinchu, Taiwan Ambassador Hotel December 5, 2006. Jim Hutchby – SRC. ITRS Emerging Research Devices Working Group. Mike Garner Intel Makoto Yoshimi SOITEC Kristin De Meyer IMEC Tak Ning IBM Philip Wong Stanford U.

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itrs emerging research devices working group
ITRS Emerging Research Devices Working Group
  • Mike Garner Intel
  • Makoto Yoshimi SOITEC
  • Kristin De Meyer IMEC
  • Tak Ning IBM
  • Philip Wong Stanford U.
  • Luan Tran Micron
  • Victor Zhirnov SRC
  • Simon Deleonibus LETI
  • Thomas Skotnicki ST Me
  • Yuegang Zhang Intel
  • Kentaro Shibahara Hiroshima U.
  • Philippe Coronel ST Me
  • Phil Kuekes HP
  • Christian Gamrat CEA
  • Dan Herr SRC
  • Dave Roberts Air Products
  • Ken Uchida Toshiba
  • Shin-ichi Takagi U. Tokyo
  • Yasuo Wada Waseda U.
  • Hiroyugi Akinaga AIST
  • Matsuo Hidaka ISTEK
  • Satoshi Sugahara Tokyo Tech
  • Tetsuya Asai Hokkaido U.
  • Wei-Xin Ni NDL
  • George Bourianoff Intel/SRC
  • Joe Brewer U. Florida
  • Toshiro Hiramoto U. Tokyo
  • Jim Hutchby SRC
  • Mike Forshaw UC London
  • Rainer Waser RWTH A
  • In Yoo Samsung
  • Lothar Risch Infineon
  • Peter Zeitzoff Freescale
  • Murali Ramachandran Freescale
  • Erik DeBenedictis SNL
  • Lou Lome IDA
  • U-In Chung Samsung
  • In-Seok Yeo Samsung
  • Ralph Cavin SRC
  • Zoran Krivokapic AMD
  • Hiroshi Mizuta Tokyo Tech
  • Seiichiro Kawamura Selete
  • Hiroshi Kotaki Sharp
  • Yuji Awano Fujitsu
  • Kojiro Yagami Sony
  • Shigenori Hayashi Matsushita
  • Yasuo Inoue Renesas Tech
  • Fumiyuki Nihei NEC

New Materials

Model Knowledge



Scope of Emerging Research Devices2006/7

New Memory

and Logic






Molecular devices

Spin states

Emerging Information Processing Concepts

emerging research devices organization component tasks 2007

Create a New Chapter in 2007

Emerging Research DevicesOrganization & Component Tasks (2007)

Emerging Research Devices




Logic and Memory




what are we looking for
Required characteristics:



Energy efficiency


Operational reliability

Room temp. operation

Preferred approach:

CMOS process compatibility

CMOS architectural compatibility

What are we looking for?

Alternative state variables (Beyond Charge State)

  • Spin state
  • Molecular state
  • Strongly correlated electron state
  • Atomic quantum state
  • Electric dipole orientation
  • Magnetic flux quanta
  • Mechanical deformation
  • Photon (intensity, phase, ..)

Alternative state variables

  • Spin–electron, nuclear, photon
  • Phase
  • Quantum state
  • Magnetic flux quanta
  • Mechanical deformation
  • Dipole orientation
  • Molecular state
critical evaluation memory

> 20

>16 - 18

>18 - 20

< 16

For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria

Max Sum = 24

Min Sum = 8

Critical EvaluationMemory
example cnt cross bar memory
Example – CNT cross-bar memory

Rueckes T. et al., SCIENCE 289 (5476): 94-97 JUL 7 2000

Moving Atoms


  • Each memory element is based on suspended crossed carbon nanotubes.
  • Cross-bar array of CNT forms mechanically bi-stable, electrostatically-switchable device elements at each cross point.
  • The memory state is read out as the junction resistance.

Expectations: n=1012 bits/cm2, f=100 GHz

memory technologies for 2007 new erd chapter
Numerical data will be updated

We will have two tables for Emerging Research Memory Technology Entries:

Capacitance-based memory technologies

Resistance-based technologies.

Put nanomechanical memory into the new tables

Transfer Nanofloating Gate Entry to PIDS/Transition Table.

Memory Technologies for 2007 new ERD Chapter
2005 itrs erd table 59 emerging research logic devices demonstrated and projected parameters




and Spin

2005 ITRS ERD: Table 59 Emerging Research Logic Devices Demonstrated and Projected Parameters
sub categories for spin and molecular devices

Domain wall manipulation

Ferromagnetic phase change (nano-domains)

Spin transport modulation

Spin torque transfer

Individual and or collective spin manipulation

Molecular devices

Crossbar coupling elements

Molecular logic elements and interconnects

Intra molecular logic elements

Sub-categories for Spin and molecular devices
critical evaluation logic

> 20

>16 - 18

>18 - 20

< 16

For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 Criteria

Max Sum = 24

Min Sum = 8

Critical EvaluationLogic
logic device conclusions

Conclusions from ERD Logic Devices Workshop(September 21, 2006)

Logic device conclusions
  • Continued analysis of alternative technology entries likely will continue to yield the same result:
    • Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels
  • Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates
    • “Plasticity” of nonlinearity may be potentially useful
supplementing cmos

Basis of Existing Assessments of Logic Devices

A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization

MF(n) – application-specific processor implementing a specific macro-function (may need specialized devices)

General Purpose Processor
















Supplementing CMOS
proposed new focus of logic section
Consider new logic technologies that supplement CMOS to provide enhanced hardware capability and can be optimally executed with alternative devices

Determine appropriate metric and compare to Si on the specialized application

Determine if proposed application contains a standard set of “macro-functions”

Understand the performance of the device in terms of its non-linear characteristics

Think in terms of heterogeneous co-processors integrated with traditional CPU

Proposed new focus of Logic Section
potential supplemental applications
Image recognition

Speech recognition

DSP (cross correlation)

Data Mining


Physical simulation

Sensory data processing (biological, physical)

Image creation

Cryptographic analysis

Potential supplemental applications
Preparing for the 2007 re-write of the ERD Chapter.

Conducted four workshops in 2006 on Emerging Research Memory, Logic, Architectures and Materials (co-sponsored by ITRS and NSF)

Considering new Technology Entries and transfers to PIDS & FEP in 2007

Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials.

Memory Section: Will add NEMS mechanical memory to section.

Divide Emerging Memory Tables into Resistive and Capacitive subcategories

Update section in 2007

Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function.

Create subcategories for key Technology Entries (e.g. Spin & Molecular logic)

Re-considering status of candidate Technology Entries (e.g. RSFQ Logic)

Re-structuring Logic Section via Emerging Logic Workshop in September.