A Cost Effective Spatial Redundancy with Data-Path Partitioning

1. A Cost Effective Spatial Redundancy with Data-Path Partitioning Shigeharu Matsusaka and Koji Inoue Fukuoka University Kyushu University/PREST

2. Outline • Introduction • Data-path Partitioning for a dependable processor • Simple Multiplexing (DPSM) • Compressed Multiplexing (DPCM) • Evaluation • Conclusions

3. Introduction • Online transaction processing • Artificial satellite • Medical treatment • Traffic control • Electric money and private information Dependability of computer systems is one of the most important design constrains!! The field where high reliability is demanded

4. Fault Internal factors External factors

5. Conventional fault detection ☺ ☹ ☹ ☺

6. Our Goal ☺ ☹ ☹ ☺ Supporting Spatial Redundancy without increasing the hardware cost!!

7. Approach: Data-Path Partitioning Data-Path Partitioning for a dependable processor: • Data-path is partitioned some narrow-width data-path • An instruction is executed in each partitioned data-path in parallel • Comparing the execution results generated from the partitioned data-path Fault is detected!!

8. Approach: Data-Path Partitioning • Implementation alternatives • Simple Multiplexing (DPSM) • Compressed Multiplexing (DPCM) Assumptions • Baseline Processor has a 32-bit Data-Path • Each 32-bit data execution can be completed in 1 clock cycle • Degree of redundancy to be realized is two or four 32-bit data-path×1 (SR1) 16-bit data-path×2 (SR2) 8-bit data-path×4 (SR4) 32-bit data-path

9. Simple Multiplexing (DPSM) CC: Clock Cycle ☹ Increasing Execution time!! ☺ Detecting Permanent fault!!

10. 0000 0000 0010 1111 0000 0000 0100 0011 1111 1111 1111 1001 0000 0000 0000 0101 0101 0110 1011 1011 1111 1111 1101 1101 0000 0000 0100 1001 0000 0000 0000 0110 Effective Bit-width The data which instruction uses • In SPECint95, 50% of instructions have both operands less than or equal to 16 bits* • Media applications mainly deal with 8-bit pixel value Bit-width to be unnecessary for each instruction execution Bit-width to be required for each instruction execution Effective bit-width Many applications have small effective bit-width!! Data-path bit-width *D. Brooks and M. Martonosi. “Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance.” HPCA, pp.13-22, 1999.

11. Compressed Multiplexing (DPCM) Effective bit-width≦Bit-width of the partitioned data-path

12. Coverage

13. Evaluation • Simulator • SimpleScalar(ver.3.0d) • Instruction-level simulation • Benchmark program • SPEC2000 benchmark suite • 164.gzip, 175.vpr, 176.gcc, 181.mcf197.parser, 255.vortex, 256.bzip • Input: small input data set Evaluation Purpose Primary evaluation for the impact of Data-Path Partitioning on processor performance Experimental setup Assumption • Perfect cache

14. Execution time ET = IC × CPI × CCT IC : Instruction Count CPI : Clock Cycle Per Instruction → 1 CCT : Clock Cycle Time → fixed value SR2：ICorg + ICgt16b × 1 SR4：ICorg + ICgt8b × 3 ICorg：The number of instructions with 32-bit data-path ICgt16b ： The number of instructions with ”Effective bit-width≧16” ICgt8b : The number of instructions with ”Effective bit-width≧8”

15. Execution time overhead (DPCM)

16. Breakdown for compressed instruction Base address is set to a large value!! Replacement of data by a compiler is necessary to reduce execution time increase

17. Conclusions • This work • Primary evaluation for the impactof data-path partitioning on processor performance • Simple Multiplexing (DPSM) • Compressed Multiplexing (DPCM) • Future work • Establishing the complete microarchitecture to support the proposed idea

18. Thank you!!