ARM Instruction Set & Assembly Language Programming

1. ARM Instruction Set & Assembly Language Programming Jianjian SONG Software Institute, Nanjing University

2. Content • ARM Architecture Introduction • ARM Instruction Set • ARM Assembly Language Programming

3. 2. ARM Architecture Introduction • ARM (Advanced RISC Machines) • 既可以认为是一个公司的名字，也可以认为是一类微处理器的通称，还可以认为是一种技术的名字。 • ARM公司是一家设计公司，是IP (Intellectual Property)供应商，靠转让设计许可证由合作伙伴生产各具特色的芯片。 • http://www.arm.com

4. ARM的特点 • ARM具有RISC体系的一般特点： • 大量寄存器 • 绝大多数操作都在寄存器中进行，通过Load/Store的在内存和寄存器间传递数据。 • 寻址方式简单 • 采用固定长度的指令格式 • 此外， • 小体积、低功耗、低成本、高性能 • 16位/32位双指令集 • 全球众多合作伙伴

5. ARM体系结构的扩充 • Thumb (Tvariant): • 16位指令集，用以改善指令密度； • Long Multiplication (M variant): • 增加两条用于长乘法操作的指令； • DSP (Evariant): • 用于DSP应用的算术运算指令集； • Jazeller (J variant): • 允许直接执行Java字节码 什么是指令密度？ 执行同等操作序列的前提下，单位内存空间所容纳的机器指令数。

6. ARM处理器系列 • ARM7系列 • ARM9系列 • ARM9E系列 • ARM10系列 • SecureCore系列 • Intel StrongARM • Intel XScale

7. 3. ARM Instruction Set • Assembly language • ARM programming model • ARM memory organization • ARM data operations • ARM flow of control

8. Assembly language • What is assembly language and why assembly language? • One-to-one with instructions (more or less). • Basic features: • One instruction per line. • Labels provide names for addresses (usually in first column). • Instructions often start in later columns. • Columns run to end of line.

9. ARM assembly language example label1 ADR r4,c LDR r0,[r4] ; a comment ADR r4,d LDR r1,[r4] SUB r0,r0,r1 ; comment

10. 31 28 27 26 25 24 21 20 19 16 15 12 11 0 cond 00 X opcode S Rn Rd Shifter-operand ARM指令的一般编码格式 opcode: 指令操作符编码 cond: 指令执行条件编码 S: 指令的操作是否影响CPSR的值 Rn: 包含第一个操作数的寄存器编码 Rd: 目标寄存器编码 Shifter_operand: 第二个操作数 符号表示： <opcode>{<cond>}{<S>} <Rd>, <Rn>, <shifter-operand>

11. ARMAddressing Modes (preliminary) • 寄存器寻址 • 例：ADD R0 , R1 , R2 ; (R1)+(R2)→R0 • 立即数寻址 • 例：ADD R3 , R3 , #2 ; (R3)+2→R3 • 寄存器间接寻址 • 例：LDR R0 , [R3] ; ((R3))→R0 • 寄存器变址 • 例：LDR R0 , [R1, #4] ; ((R1)+4)→R0 • 相对寻址 • 例：B rel ; (PC)+offset→PC

12. Pseudo-ops • Some assembler directives don’t correspond directly to instructions: • Define current address. • Reserve storage. • Constants.

13. N Z C V ARM programming model r0 r8 r1 r9 0 31 r2 r10 CPSR r3 r11 r4 r12 r5 r13 r6 r14 r7 r15 (PC)

14. ARM status bits • Every arithmetic, logical, or shifting operation sets CPSR bits: • N (negative), Z (zero), C (carry), V (overflow). • Examples: • -1 + 1 = 0: NZCV = 0110. • 231-1+1 = -231: NZCV = 0101.

15. ARM data types • Word is 32 bits long. • Word can be divided into four 8-bit bytes. • ARM addresses can be 32 bits long. • Address refers to byte. • Address 4 starts at byte 4. • Can be configured at power-up as either little- or big-endian mode.

16. Instructions Overview • Data instructions • Load/Store instructions • Move Instructions • Comparison instructions • Branch instructions

17. ARM data instructions • Basic format: ADD r0,r1,r2 • Computes r1+r2, stores in r0. • Immediate operand: ADD r0,r1,#2 • Computes r1+2, stores in r0.

18. ADD, ADC : add (w. carry) SUB, SBC : subtract (w. carry) RSB, RSC : reverse subtract (w. carry) MUL, MLA : multiply (and accumulate) AND, ORR, EOR BIC : bit clear LSL, LSR : logical shift left/right ASL, ASR : arithmetic shift left/right ROR : rotate right RRX : rotate right extended with C ARM data instructions

19. Data operation varieties • Logical shift: • fills with zeroes. • Arithmetic shift: • fills with zeroes or ones. • RRX performs 33-bit rotate, including C bit from CPSR above sign bit.

20. ARM load/store instructions • LDR, LDRH, LDRB : load (half-word, byte) • STR, STRH, STRB : store (half-word, byte) • Addressing modes: • register indirect : LDR r0,[r1] • with second register : LDR r0,[r1,-r2] • with constant : LDR r0,[r1,#4]

21. ARM ADR pseudo-op • Cannot refer to an address directly in an instruction. • Generate value by performing arithmetic on PC. • ADR pseudo-op generates instruction required to calculate address: ADR r1,FOO

22. 伪指令 • ADR • ADR{cond} register, expr • 将基于PC的地址值或基于寄存器的地址值读取到寄存器中 • 汇编替换成一条指令 • ADRL • ADRL{cond} register, expr • ADRL伪指令比ADR读取更大的地址范围。 • 汇编替换为两条指令 • LDR • LDR{cond} register, =[expr | label_expr] • 将一个32位的常数或地址值读取到寄存器中 • NOP • 空操作，如MOV R0, R0

23. ARM move instructions • MOV, MVN : move (negated) MOV r0, r1 ; r0 <- r1

24. ARM comparison instructions • CMP : compare • CMN : negated compare • TST : bit-wise test • TEQ : bit-wise negated test • These instructions set only the NZCV bits of CPSR.

25. ARM branch instructions • B: Branch • BL: Branch and Link

26. Example: C assignments • C: x = (a + b) - c; • Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b, reusing r4 LDR r1,[r4] ; get value of b ADD r3,r0,r1 ; compute a+b ADR r4,c ; get address for c LDR r2,[r4] ; get value of c

27. C assignment, cont’d. SUB r3,r3,r2 ; complete computation of x ADR r4,x ; get address for x STR r3,[r4] ; store value of x

28. Example: C assignment • C: y = a*(b+c); • Assembler: ADR r4,b ; get address for b LDR r0,[r4] ; get value of b ADR r4,c ; get address for c LDR r1,[r4] ; get value of c ADD r2,r0,r1 ; compute partial result ADR r4,a ; get address for a LDR r0,[r4] ; get value of a

29. C assignment, cont’d. MUL r2,r2,r0 ; compute final value for y ADR r4,y ; get address for y STR r2,[r4] ; store y

30. Example: C assignment • C: z = (a << 2) | (b & 15); • Assembler: ADR r4,a ; get address for a LDR r0,[r4] ; get value of a MOV r0,r0,LSL 2 ; perform shift ADR r4,b ; get address for b LDR r1,[r4] ; get value of b AND r1,r1,#15 ; perform AND ORR r1,r0,r1 ; perform OR

31. C assignment, cont’d. ADR r4,z ; get address for z STR r1,[r4] ; store value for z

32. Additional addressing modes • Base-plus-offset addressing: LDR r0,[r1,#16] • Loads from location r1+16 • Auto-indexing increments base register: LDR r0,[r1,#16]! • Post-indexing fetches, then does offset: LDR r0,[r1],#16 • Loads r0 from r1, then adds 16 to r1.

33. ARM flow of control • All operations can be performed conditionally, testing CPSR: • EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE • Branch operation: B #100 • Can be performed conditionally.

34. Example: if statement • C: if (a < b) { x = 5; y = c + d; } else x = c - d; • Assembler: ; compute and test condition ADR r4,a ; get address for a LDR r0,[r4] ; get value of a ADR r4,b ; get address for b LDR r1,[r4] ; get value for b CMP r0,r1 ; compare a < b BGE fblock ; if a >= b, branch to false block

35. If statement, cont’d. ; true block MOV r0,#5 ; generate value for x ADR r4,x ; get address for x STR r0,[r4] ; store x ADR r4,c ; get address for c LDR r0,[r4] ; get value of c ADR r4,d ; get address for d LDR r1,[r4] ; get value of d ADD r0,r0,r1 ; compute y ADR r4,y ; get address for y STR r0,[r4] ; store y B after ; branch around false block

36. If statement, cont’d. ; false block fblock ADR r4,c ; get address for c LDR r0,[r4] ; get value of c ADR r4,d ; get address for d LDR r1,[r4] ; get value for d SUB r0,r0,r1 ; compute a-b ADR r4,x ; get address for x STR r0,[r4] ; store value of x after ...

37. Example: Conditional instruction implementation ; true block MOVLT r0,#5 ; generate value for x ADRLT r4,x ; get address for x STRLT r0,[r4] ; store x ADRLT r4,c ; get address for c LDRLT r0,[r4] ; get value of c ADRLT r4,d ; get address for d LDRLT r1,[r4] ; get value of d ADDLT r0,r0,r1 ; compute y ADRLT r4,y ; get address for y STRLT r0,[r4] ; store y

38. Example: switch statement • C: switch (test) { case 0: … break; case 1: … } • Assembler: ADR r2,test ; get address for test LDR r0,[r2] ; load value for test ADR r1,switchtab ; load address for switch table LDR r15,[r1,r0,LSL #2] ; index switch table switchtab DCD case0 DCD case1 ...

39. Example: FIR filter • C: for (i=0, f=0; i<N; i++) f = f + c[i]*x[i]; • Assembler ; loop initiation code MOV r0,#0 ; use r0 for I MOV r8,#0 ; use separate index for arrays ADR r2,N ; get address for N LDR r1,[r2] ; get value of N MOV r2,#0 ; use r2 for f

40. FIR filter, cont’.d ADR r3,c ; load r3 with base of c ADR r5,x ; load r5 with base of x ; loop body loop LDR r4,[r3,r8] ; get c[i] LDR r6,[r5,r8] ; get x[i] MUL r4,r4,r6 ; compute c[i]*x[i] ADD r2,r2,r4 ; add into running sum ADD r8,r8,#4 ; add one word offset to array index ADD r0,r0,#1 ; add 1 to i CMP r0,r1 ; exit? BLT loop ; if i < N, continue

41. ARM subroutine linkage • Branch and link instruction: BL foo • Copies current PC to r14. • To return from subroutine: MOV r15,r14

42. Nested subroutine calls • Nesting/recursion requires coding convention: f1 LDR r0,[r13] ; load arg into r0 from stack ; call f2() STR r13!,[r14] ; store f1’s return adrs STR r13!,[r0] ; store arg to f2 on stack BL f2 ; branch and link to f2 ; return from f1() SUB r13,#4 ; pop f2’s arg off stack LDR r13!,r15 ; restore register and return

43. Summary • Load/store architecture • Most instructions are RISCy, operate in single cycle. • Some multi-register operations take longer. • All instructions can be executed conditionally.

44. 4. ARM Assembly Language Programming • Why and when to use? • AT&Tformat and Intel format • Grammar of ARM assembly language • Examples

45. Why and when to use? • 操作系统内核中的底层程序直接与硬件打交道，需要用到的专用指令。 • CPU中的特殊指令 • 频繁使用代码的时间效率 • 程序的空间效率(如操作系统的引导程序) Refer to “Linux内核源代码情景分析”(浙江大学出版社)1.5节

46. AT&T format and Intel format

47. Grammar of ARM assembly language • 语句 • 程序格式

48. 语句 • 语句 • 指令 • 伪操作 • 宏 • 语句格式 • { symbol } { instruction | directive | pseudo-instruction } { ;comment }

49. 伪操作 • 符号定义伪操作 • 数据定义伪操作 • 汇编控制伪操作 • 框架描述伪操作 • 信息报告伪操作 • 其它伪操作

50. 关于变量的伪操作 • 声明一个全局变量，并初始化 • GBLA, GBLL, GBLS • 声明一个局部变量，并初始化 • LCLA, LCLL, LCLS • 变量赋值 • SETA, SETL, SETS