Theory and Fabrication of Integrated Circuits. Lecture. No. 04 Prof. Dr. Wajiha Shah. Core concepts for the production of integrated circuits:. Thermal Oxidation Photolithography Etching Dopant Diffusion Metal Evaporation Electrical Testing. Thermal Oxidation .
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Lecture. No. 04
Prof. Dr. Wajiha Shah
Silicon is the dominant semiconductor used in integrated circuit processing, in large part due to its ability to form a robust (tough) native oxide.
This oxide is used for multiple purposes in the fabrication of ICs:
Of particular importance in semiconductor processing is cleanliness. For oxidation, cleanliness must be targeted to the molecular level. A specialized process called the RCA Clean is implemented before oxidation to remove
After cleaning with the RCA clean, silicon wafers are placed into a high temperature furnace (900ºC < T < 1200ºC) in the presence of oxygen or water where the following reaction occurs:
Si + O2→ SiO2
Si + 2H2O → SiO2 +H2
By controlling temperature and oxidation time precisely, oxide thickness can be predicted and controlled accurately.
ECE444 students performing an oxidation process in a high temperature furnace.
After oxidation, the silicon wafer is completely covered with silicon dioxide. This oxide will prevent dopants from reaching the underlying silicon wafer.
In order to create integrated circuits, the silicon wafer must be doped with impurities (boron and phosphorus are the most common) selectively – this is accomplished by removing the oxide in specific areas so the dopants are allowed to diffuse (movement due to high temperature) into the exposed silicon.
Selective removal of the oxide is performed using
Photolithography is very much like taking a picture:
But photolithography is binary – either the film is exposed or not exposed; there are no shades of gray.
Mask or Reticle:
The mask is tranparent plate of fused silica (high purity glass) with an optically opaque film applied to one surface. A detailed layout of the circuit is created using computer aided design (CAD) software, and this pattern is etched into the opaque film. The etched film on the mask creates the hard copy of the circuit pattern.
The mask/reticle is then used to transmit UV light in the pattern of the circuit.
CAD full adder layout
Isometric detail view of the ECE444 CAD layout
Photoresist (an organic polymer sensitive to UV light and resistant to attack by acids) is applied to the oxidized wafer using a photoresist spinner. This process uses centrifugal force from high speed rotation of the wafer.
The PR is applied as a small puddle in the center of the wafer. When the wafer spins, the PR spreads out over the wafer due to centrifugal force. After spinning, a uniform layer of PR remains on the surface.
ECE444 student dispensing photoresist onto an oxidized silicon wafer. Note the yellow cast to the picture – short wavelength light (green, blue, violet, and ultraviolet) exposes PR, so it has been filtered out of the room light, leaving only red, orange, and yellow to see with!
Alignment and Exposure:
The PR coated wafer is placed into a system (mask aligner or ‘stepper’) which allows the mask to be aligned to the wafer. After alignment, the system opens a shutter to allow UV light to illuminate the PR through the mask for a controlled period of time.
The PR which is exposed to UV light undergoes a photochemical reaction to make the PR more acidic (indene carboxylic acid is produced).
ECE444 student loading PR coated wafer into an Ultratech 1000WF Step and Repeat Projection Alignment system (also known as a ‘stepper’).
After the wafer is exposed to UV light through the mask, the acidic regions of PR are removed by dipping the wafer into an alkaline (base) developing solution. The acidic PR reacts chemically with the basic developer to form water soluble salts that dissolve in the developer.
At this point the mask image can be seen in the PR (remember that the PR was illuminated with UV light through the mask, so only light in the shape of the circuit reaches the PR – the rest of the PR did not change!).
Note: the image from the mask has only been transferred to the PR. The PR will be used as a mask for etching the underlying oxide in an acid bath.
The previous steps produced a pattern in the PR layer coating the oxidized wafer. This patterned PR will now be used for selectively etching the oxide areas that are exposed.
The patterned, PR coated wafer is placed into a hydrofluoric (HF) acid bath to remove the exposed oxide. HF will react chemically with the oxide to form water soluble products that dissolve in the water used to dilute the acid.
When the oxide is etched away, the silicon beneath the oxide can be seen. Fortunately, HF does not react with silicon (this is ideal – the HF is selective with regards to the two materials present on the wafer).
The PR is then removed, leaving a permanent pattern etched into the oxide.
Oxidized and etched 100mm diameter wafer fabricated in the ECE444 laboratory. Mask level 1 used for photolithography. Purple areas are silicon dioxide, silver areas are exposed silicon.
Silicon is a column IV element – this means there are four electrons in the outermost shell of the atom. It is these electrons that are used when bonding to other atoms. In a wafer, each silicon atom bonds to four other silicon atoms (each Si-Si bond shares one electron). So in an intrinsic (pure) silicon wafer, all the electrons in the outer shell are part of a bond – they are ‘stuck’ between the bonded silicon atoms.
In order for current to flow in a material there must be ‘loose’ electrons. But all the electrons in silicon are working at holding the atoms together, which means it is not a good conductor of current.
So what can be done to allow the silicon to conduct current more easily? Free ‘carriers’ of current must be added. The goal is to find an element about the same size as a silicon atom so that it fits together well with the silicon, but with more electrons in its outer shell.
In the periodic table, the closer elements are to each other, the more similar they are. So the best candidates would come from column V (which have five outer shell electrons). The element closest to silicon in column V is phosphorus.
If phosphorus is inserted into the silicon wafer in a certain way, it will take the place of a silicon atom and bond with its four neighbor silicon atoms. After bonding, phosphorus has an electron left over that is not bonded to a silicon atom. It turns out this extra electron is not strongly held by the phosphorus atom any more, so it can be removed easily. This electron then becomes a ‘carrier’ for current – it is free to move around the wafer. So the conductivity of the silicon wafer increases. This type of silicon ‘doped’ with phosphorus is called an n-type semiconductor.
Extending this idea of inserting an element with a different number of valence electrons, a column III element (such as boron) could be added to the silicon wafer. In this case, the boron will try to bond with four silicon atoms, but it only has three electrons to bond with. This means there is an incomplete bond with one of the silicon atoms – a ‘hole’ where an electron would normally be. This ‘hole’ behaves much like an electron and can move around the wafer, but with an opposite charge (+). So a different type of current carrier is present in the wafer that increases the wafer’s conductivity. This type of silicon ‘doped’ with boron is called a p-type semiconductor.
By adding impurities to silicon, the conductivity increases. This conductivity can be adjusted by the amount of impurity added.
Now for the interesting part - when n-type silicon comes into contact with p-type silicon. A built-in potential (voltage) develops that must be overcome before current can flow from the n-type to p-type regions.
Think of carriers as being able to only move across a flat surface or down a slope. The built in potential is a hill that the carrier can not go up. So in order for the carrier to keep moving, the low part must be pushed up to be level or higher than the top of the hill. In the case of an n-type / p-type junction, the energy to push up the low side comes in the form of a voltage applied to the wafer. The voltage is used to ‘push up’ the ‘ground’ on the low side of the hill before current flows from n-type to p-type regions.
But if the voltage is reversed, the energy is used to push the low side lower while keeping the high side at the same height! That means the carrier probably won’t ever make it up the higher hill, so it is stuck (no current flows).
So when n-type silicon is brought into contact with p-type silicon (a pn junction), current can flow in only one direction. This is the fundamental semiconductor device – a pn junction diode – a one way switch for current.
The devices used in integrated circuits are specialized combinations of pn junctions. The junctions are formed by the addition of impurity atoms from columns III and V of the periodic table into the silicon wafer through diffusion.
The goal of the dopant predeposition diffusion is to move dopant atoms from a source to the wafer, and then allow the dopants to diffuse into the wafer.
The source of dopant can be in several forms – solid (boron nitride and phosphorus oxide ceramic discs), liquid (boron tribromide and POCl3), or gas (diborane or phosphine).
In order for the dopants to move into the silicon, they must be given energy, usually in the form of heat. In order for the diffusion to occur in a reasonable time, the temperature must be very high (900ºC At this temperature the dopant (in the form of an oxide) reacts with the exposed silicon surface to form a highly doped glass. It is from this glass that the dopants can then diffuse into the wafer. The first dopant diffusion in the ECE444 process is a boron diffusion (the wafer is originally doped at a low level with phosphorus). This diffusion forms the first pn junctions selectively on the wafer through the openings in the oxide defined by photolithography. ECE444 Diffusion furnace
At this temperature the dopant (in the form of an oxide) reacts with the exposed silicon surface to form a highly doped glass. It is from this glass that the dopants can then diffuse into the wafer.
The first dopant diffusion in the ECE444 process is a boron diffusion (the wafer is originally doped at a low level with phosphorus). This diffusion forms the first pn junctions selectively on the wafer through the openings in the oxide defined by photolithography.
ECE444 Diffusion furnace
After the predeposition diffusion the dopants are situated close to the surface of the wafer. However, they must diffuse even farther to lower the overall concentration in order for some of the devices to work properly.
The first diffusion (predeposition) introduces dopants into the wafer.
The second diffusion (drive) redistributes the dopants and allow the dopants to diffuse into the wafer more deeply (up to ~3 micrometers)
In addition, oxygen and water vapor are introduced during the drive diffusion to grow a new oxide over the areas which were exposed to bare silicon during the photolithography process. This new oxide can be patterned again so that other selective diffusion processes can be performed to create other types of devices.
Diffusion (Ion Implantation)Repeat the process…
At this point, the process of oxidation-photolithography-etching-diffusion can be repeated to produce the various types of electronic devices required for a circuit.
Some modern processes may require more than 20 iterations of this sequence!
The following slides show the rest of the processes performed in the ECE444 lab.
Gate Oxide Formation
Electrical contact vias (holes) to silicon
After all diffusion and oxidation steps are completed, metal is deposited onto the surface of the wafer. This metal is used to ‘wire’ the devices fabricated in the silicon together.
The wafers are put into a large chamber and the air is pumped out of the system. A piece of aluminum located on a tungsten ‘boat’ in the system is heated to high temperature, causing the aluminum to melt and evaporate. The evaporated aluminum will solidify into a thin film when it touches the silicon wafer.
Thermal evaporation vacuum system used in the ECE444 laboratory. This tool was designed and built for an independent study project.
After metallization, the wafer is completely covered by the aluminum.
It must be patterned and etched to form the actual ‘wires’ connecting individual devices into a circuit.
Wafer after aluminum evaporation
Steps to create ECE444 wafer:
Time to see if it works…
After completion of the wafer, it must be tested to verify operation.
The devices fabricated are extremely small (some dimensions are as small a 1micrometer!), so specialized probes are used to make electrical contact.
Once contact is made, several different instruments are used to measure electrical performance.
ECE444 Probe station
Example of electrical data from a device fabricated in the ECE444 laboratory