Chapter 5 Register Transfer Languages

Chapter 5 Register Transfer Languages

Chapter 5 Register Transfer Languages

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Presentation Transcript

1. Chapter 5Register Transfer Languages

2. Micro-operations RTL RTL specifications Realizing RTL specifications VHDL Chapter Outline

3. Specify data transfer Do not specify conditions under which transfers occur Do not specify hardware implementation Micro-operations

4. Specify micro-operations and when they occur Format: conditions: micro-operations Register Transfer Language

5. α: X  Y, Y  Z Simultaneous Data Transfers Q D

6. α: X  Y, X  Z Invalid Simultaneous Transfers

7. α: X  0 β: X  1 Loading Constant Values into Registers

8. Making Transfers Mutually Exclusive

9. α: X  Y Multi-bit Data Transfers

10. Bit and Bit-range Transfers

11. Arithmetic and Logical Micro-operations

12. Shift Micro-operations

13. Specifying Digital Components: D Flip-Flop

14. Specifying Digital Components: JK Flip-Flop

15. Specifying Digital Components: Left Shift Register

16. Specifying Simple Systems

17. System Implementation – Data Paths

18. System Implementation – Data Paths and Control

19. System Implementation Using a Bus and 3-State Buffers

20. Counts up when U = 1 Count sequence: 000 001  010  011  100  101  000 … V is 3-bit output = count value C is 1-bit output = 1 when V = 000 Modulo 6 Counter

21. Modulo 6 Counter State Table 1 1 1 1 1 1

22. Modulo 6 Counter State Diagram

23. Modulo 6 Counter RTL Specification

24. Modulo 6 Counter System Implementation

25. Modulo 6 Counter Another System Implementation

26. C = 1 when car is at toll booth I[1..0] indicates coin input Outputs R, G, A: Car in toll booth, toll not fully paid: R = 1 Toll paid: G = 1 Car left without paying full toll: R = 1, A = 1 Toll Booth Controller

27. Toll Booth Controller States

28. Toll Booth Controller State Table

29. Toll Booth Controller State Diagram

30. Toll Booth Controller State Assignments

31. Converting State Transitions to RTL Code

32. Converting State Transitions to RTL Code

33. Toll Booth Controller RTL Specification (excluding outputs)

34. Toll Booth Controller RTL Specification (outputs)

35. Formal syntax – portable Platform independent Design for PLDs, ASICs, or custom chips Simulate designs Different levels of abstraction VHDL – VHSIC Hardware Description Language

36. Library section Entity section Architecture section VHDL Design Structure

37. library IEEE; use IEEE.std_logic_1164.all; VHDL Library Section

38. VHDL Entity Section

39. VHDL Architecture Section

40. Modulo 6 counter Designed as a state machine VHDL – High Level of Abstraction

41. Modulo 6 Counter – Library and Entity Sections

42. Modulo 6 Counter – One State

43. Architecture Section – State Generation

44. Architecture Section – State Generation (continued)

45. Architecture Section – State Transition

46. VHDL – Low Level of Abstraction

47. Components Timing Simulation VHDL – Advanced Capabilities