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Chapter 14. Arithmetic Circuits (I): Adder Designs. Rev. 1.0 05/12/2003 Rev. 2.0 06/05/2003 Rev. 2.1 06/12/2003. A Generic Digital Processor. Building Blocks for Digital Architectures. Arithmetic and Unit. Bit-sliced datapath. ( adder, multiplier, shifter, comparator, etc.). -.

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### Chapter 14

Arithmetic Circuits (I):

Rev. 1.0 05/12/2003

Rev. 2.0 06/05/2003

Rev. 2.1 06/12/2003

Arithmetic and Unit

Bit-sliced datapath

-

Memory

- RAM, ROM, Buffers, Shift registers

Control

- Finite state machine (PLA, random logic.)

- Counters

Interconnect

- Switches

- Arbiters

- Bus

Itanium has 6 integer execution units like this

Fetzer, Orton, ISSCC’02

Generate (G) = AB

Propagate (P) = A

B

Å

Delete =

A

B

CMOS Implementation

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A

B

Å

Delete =

A

B

S

C

D and P

Can also derive expressions for

and

based on

o

Note that we will be sometimes using an alternate definition for

+

Propagate (P) = A

B

B

A

B

A

B

A

B

0

0

1

1

2

2

3

3

C

C

C

C

C

i

,0

o

,0

o

,1

o

,2

o

,3

FA

FA

FA

FA

=

(

C

)

i

,1

S

S

S

S

0

1

2

3

Critical

Path

Worst-case delayis linear with the number of bits

td = O(N)

• Propagation delay (or critical path) is the worst-case delay over all possible input patterns

• A= 0001, B=1111, trigger the worst-case delay

• A: 0  1, and B= 1111 fixed to set up the worst-case delay transition.

28 Transistors

• Logic effort of Ci is reduced to 2 (c.f., A and B signals)

• Ci is late arrival signal  near the output signal

• Co needs to be inverted  Slow down the ripple propagate

• Exploit Inversion Property

• Reduce One inverter delay in each Full-adder (FA) unit

Exploring the “Self-Duality” of the Sum and Carry functions

• The NMOS and PMOS chains are completely symmetrical

• A maximum of two series transistors can be observed in the carry-generation circuitry  for good speed.

• When laying out the cell, the most critical issue is the minimization of the capacitance at node Co.

• The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

• The transistors connected to Ci are placed closest to the output.

Truth Table

A=0: Pass B Signal

A=1: Inverting B Signal

• Same delay for Sum and Carry  Multiplier design

Static Circuits

Dynamic Circuits

Dynamic

Static

Mux-

based

4-bit

Section

sum<n>

• Dynamic stage

• When CLK is low, the output node is pre-charged by the p pull-up transistor.

• When CLK goes high, the pull-down transistor turns on.

• If carry generate G=AB is true  the output node discharges.

• If carry propagate P=A+B is true  a previous carry may be coupled to the output node, conditionally discharging it.

• Static stage

• This requires P to be generated as AB

G

P

G

P

G

P

G

0

1

0

1

2

2

3

3

C

C

C

C

C

i,0

o,3

o,0

o,1

o,2

Also called Carry-Skip

FA

FA

FA

FA

P

G

P

G

P

G

P

G

0

1

0

1

2

2

3

3

BP=P

P

P

P

o

1

2

3

C

C

C

C

i,0

o,0

o,1

o,2

r

e

FA

FA

FA

FA

x

e

C

l

o,3

p

i

t

l

u

M

Idea: If ( )

elseKillor Generate

then C

= C

O,3

I,0

Wired OR

• The control signals T1,T2,and T3 shown in Fig6(b) are generated by:

• T1 = -(P0P1P2)P3

• T2 = -P3

• T3 = P0P1P2P3

Fig6. Manchester adder with carry bypass: (a) simple (b) conflict free

• The worst case propagation time of a Manchester adder can be improved by bypassing the four stages if all carry-propagate signals are true.

• Fig. 6(b) uses a “conflict -free” bypass circuit, which improves the speed by using a 3-input multiplexer that prevents conflicts at the wired OR node in the adder.

• In Fig. 6(b), the inverter presented on the Cin signal has been moved to the center of the carry chain to improve speed.

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

M bits form a Section  (N/M) Bypass Stages

Wordlength (N) > 4~8 is better for Bypass Adder

P,G

"0" Carry Propagation

"0"

"1"

"1" Carry Propagation

C

C

o,k-1

2-to-1 Multiplexer

o,k+3

Carry Vector

Sum Generation

N-bit adder with P stages: 1st stage adds M bits, 2nd has (M+1) bits

The linear growth of adder carry-delay with the size of the input word for n-bit adder maybe improved by calculation the carries to each stage in parallel.

Carry of the ith stage ---

Expanding:

For four stages, the appropriate term:

C0= G0 + P0CI

C1= G1 + P1G0 + P1P0CI

C2= G2 + P2G1 + P2P1G0 + P2P1P0CI

C3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0CI

Static CMOS Circuits input word for n-bit adder maybe improved by

All the way:

Dynamic CMOS Circuits input word for n-bit adder maybe improved by

• The worst-case delay path in this circuit has six

• n-transistor in series.

• Size and fan-in of the gates needed to implement this carry-lookahead scheme can clearly get out of hand

• Number of stages of lookahead is usually limited to about 4.

• The circuit and layout are quite irregular compared with ripple adder designs.

Summary input word for n-bit adder maybe improved by

• Datapath designs are fundamentals for high-speed DSP, Multimedia, Communication digital VLSI designs.

• Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint.

• For details, check “Advanced VLSI” notes, or “Computer Arithmetic” textbooks