Chapter 14. Arithmetic Circuits (I): Adder Designs. Rev. 1.0 05/12/2003 Rev. 2.0 06/05/2003 Rev. 2.1 06/12/2003. A Generic Digital Processor. Building Blocks for Digital Architectures. Arithmetic and Unit. Bitsliced datapath. ( adder, multiplier, shifter, comparator, etc.). .
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Arithmetic Circuits (I):
Adder Designs
Rev. 1.0 05/12/2003
Rev. 2.0 06/05/2003
Rev. 2.1 06/12/2003
Building Blocks for Digital Architectures
Arithmetic and Unit
Bitsliced datapath
(adder, multiplier, shifter, comparator, etc.)

Memory
 RAM, ROM, Buffers, Shift registers
Control
 Finite state machine (PLA, random logic.)
 Counters
Interconnect
 Switches
 Arbiters
 Bus
Itanium has 6 integer execution units like this
Fetzer, Orton, ISSCC’02
CMOS Implementation
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A
B
Å
Delete =
A
B
S
C
D and P
Can also derive expressions for
and
based on
o
Note that we will be sometimes using an alternate definition for
+
Propagate (P) = A
B
B
A
B
A
B
A
B
0
0
1
1
2
2
3
3
C
C
C
C
C
i
,0
o
,0
o
,1
o
,2
o
,3
FA
FA
FA
FA
=
(
C
)
i
,1
S
S
S
S
0
1
2
3
CarryRipple AdderCritical
Path
Worstcase delayis linear with the number of bits
tadder = (N1)tcarry + tsum
td = O(N)
28 Transistors
Exploring the “SelfDuality” of the Sum and Carry functions
G
P
G
P
G
P
G
0
1
0
1
2
2
3
3
C
C
C
C
C
i,0
o,3
o,0
o,1
o,2
Also called CarrySkip
FA
FA
FA
FA
P
G
P
G
P
G
P
G
0
1
0
1
2
2
3
3
BP=P
P
P
P
o
1
2
3
C
C
C
C
i,0
o,0
o,1
o,2
r
e
FA
FA
FA
FA
x
e
C
l
o,3
p
i
t
l
u
M
CarryBypass Adder DesignIdea: If ( )
elseKillor Generate
then C
= C
O,3
I,0
Wired OR
Fig6. Manchester adder with carry bypass: (a) simple (b) conflict free
tadder = tsetup + Mtcarry + (N/M1)tbypass + (M1)tcarry + tsum
M bits form a Section (N/M) Bypass Stages
Wordlength (N) > 4~8 is better for Bypass Adder
P,G
"0" Carry Propagation
"0"
"1"
"1" Carry Propagation
C
C
o,k1
2to1 Multiplexer
o,k+3
Carry Vector
Sum Generation
CarrySelect AdderFig7. Carryselect adder:(a) basic architecture (b) 32bit carryselect adder example
The linear growth of adder carrydelay with the size of the input word for nbit adder maybe improved by calculation the carries to each stage in parallel.
CarryLookahead AddersCarryLookahead Adders (cont’d) input word for nbit adder maybe improved by
Carry of the ith stage 
Expanding:
For four stages, the appropriate term:
C0= G0 + P0CI
C1= G1 + P1G0 + P1P0CI
C2= G2 + P2G1 + P2P1G0 + P2P1P0CI
C3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0CI
Fig1. Generic carrylookahead adder
Expanding Lookahead equations:
All the way:
Dynamic CMOS Circuits input word for nbit adder maybe improved by
CarryLookahead Adders input word for nbit adder maybe improved by