Programmable Logic Devices. Dense array of. Dense array of. AND gates. Product. OR gates. terms. Prgrammable Logic Organization. Prefabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates. Inputs. Outputs.
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Dense array of
AND gates
Product
OR gates
terms
Prgrammable Logic OrganizationInputs
Outputs
Programmable Array Block Diagram for Sum of Products Form
PAL
PROM
PLA
AND ARRAY
PROG.
FIXED
PROG.
OR ARRAY
FIXED
PROG.
PROG.
Basic Programmable Logic OrganizationsF1 = A C + A B
F2 = B C + A B
F3 = B C + A
Product
Inputs
Outputs
t
erm
F
F
F
F
A
B
C
0
1
2
3
0
1
1
0
A B
1
1

Reuse
0
0
0
1
B C

0
1
of
0
1
0
0
A C
1

0
t
erms
1
0
1
0
B C

0
0
1
0
0
1
A
1


PLA Logic ImplementationKey to Success: Shared Product Terms
Equations
Example:
Personality Matrix
Input Side:
1 = asserted in term
0 = negated in term
 = does not participate
Output Side:
1 = term connected to output
0 = no connection to output
C
A
F3
F0
F2
F1
PLA Logic ImplementationExample Continued  Unprogrammed device
All possible connections are available
before programming
C
A
AB
BC
AC
BC
A
F3
F0
F2
F1
PLA Logic ImplementationExample Continued 
Programmed part
Unwanted connections are "blown"
Note: some array structures
work by making connections
rather than breaking them
AB
AB
Notation for implementing
F0 = A B + A B
F1 = C D + C D
CD
CD
CD+CD
AB+AB
PLA Logic ImplementationUnprogrammed device
Alternative representation
Shorthand notation
so we don\'t have to
draw all the wires!
X at junction indicates
a connection
Programmed device
C
B
ABC
A
B
C
A
B
C
ABC
ABC
ABC
ABC
ABC
ABC
ABC
F1
F2
F3
F4
F5
F6
PLA Logic ImplementationDesign Example
Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C
F3 = A B C
F4 = A + B + C
F5 = A B C
F6 = A B C
What is difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
PAL concept — implemented by Monolithic Memories
AND array is programmable, OR array is fixed at fabrication
A given column of the OR array
has access to only a subset of
the possible product terms
PLA concept — Both AND and OR arrays are programmable
B
C
D
W
X
Y
Z
A
A
AB
AB
0
0
0
0
0
0
0
0
00
01
11
10
00
01
11
10
0
0
0
1
0
0
0
1
CD
CD
0
0
1
0
0
0
1
1
00
0
0
X
1
00
0
1
X
0
0
0
1
1
0
0
1
0
0
1
0
0
0
1
1
0
01
0
1
X
1
01
0
1
X
0
0
1
0
1
1
1
1
0
D
D
0
1
1
0
1
0
1
0
0
1
X
X
0
0
X
X
11
11
0
1
1
1
1
0
1
1
C
C
1
0
0
0
1
0
0
1
10
10
1
0
0
1
1
0
0
0
0
1
X
X
0
0
X
X
1
0
1
0
X
X
X
X
1
0
1
1
X
X
X
X
B
B
1
1
0
0
X
X
X
X
Kmap for
W
Kmap for
X
1
1
0
1
X
X
X
X
1
1
1
0
X
X
X
X
A
A
1
1
1
1
X
X
X
X
AB
AB
00
01
11
10
00
01
11
10
CD
CD
00
0
1
X
0
00
0
0
X
1
X
01
01
0
1
0
0
X
0
1
D
D
1
1
X
X
0
1
X
X
11
11
C
C
W = A + B D + B C
X = B C
Y = B + C
Z = A B C D + B C D + A D + B C D
10
10
1
1
X
X
1
0
X
X
B
B
Kmap for
Y
Kmap for
Z
PAL Logic ImplementationDesign Example: BCD to Gray Code Converter
Kmaps
Truth Table
Minimized Functions:
A
BD
BC
0
BC
W = A + B D + B C
X = B C
Y = B + C
Z = A B C D + B C D + A D + B C D
0
0
0
B
C
0
0
A B C D
BCD
AD
BCD
W X Y Z
PAL Logic ImplementationProgrammed PAL:
Minimized Functions:
4 product terms per each OR gate
A
A
1
B
4
C
B
D
2
3
W
D
B
3
C
B
2
D
C
4
Z
D
1
D
5
A
B
2
X
1
B
1
C
3
C
D
C
1: 7404 hex inverters
2
Y
B
1
B
2,5: 7400 quad 2input NAND
3: 7410
t
ri 3input NAND
4: 7420 dual 4input NAND
PAL Logic ImplementationCode Converter Discrete Gate Implementation
4 SSI Packages vs. 1 PLA/PAL Package!
A
A
AB
AB
ABCD
00
01
11
10
00
01
11
10
CD
CD
00
00
1
0
0
0
0
1
1
1
ABCD
01
01
0
1
0
0
1
0
1
1
ABCD
D
D
ABCD
11
11
0
0
1
0
1
1
0
1
C
C
10
10
0
0
0
1
1
1
1
0
AC
AC
B
B
Kmap for
EQ
Kmap for
NE
BD
A
A
BD
AB
AB
00
01
11
10
00
01
11
10
CD
CD
ABD
00
00
0
0
0
0
0
1
1
1
BCD
1
0
0
0
0
0
1
1
01
01
ABC
D
D
11
1
1
0
1
11
0
0
0
0
BCD
C
C
10
1
1
0
0
10
0
0
1
0
B
B
Kmap for
L
T
Kmap for
GT
EQ
NE
LT
GT
PLA Logic ImplementationAnother Example: Magnitude Comparator
OLMC (Output Logic MacroCell) has OR, FF, output multiplexer and I/O control logic.
Note that OLMC output is fed back to input matrix for use in other OLMCs.
CLK
T
S
M
U
X
11
10
01
00
vcc
AC0
AC1(n)
P
T
M
U
X
O
1
O
M
U
X
O
1
I/O(n)
Q
FROM
AND
ARRAY
D
Q
XOR(n)
F
M
U
X
10
11
01
00
FEEDBACK
FROM
ADJ. STAGE
OUTPUT(m)
ACO
AC1(m)
AC1(n)
CLK
OE
GAL16V8 OLMC Structure
Simple mode (combinational output)
combinational output
combinational output with feedback
dedicated input
Complex mode
combinational output, with feedback
combinational input from another OLMC Registered mode: active (low, high): Q’ is feedback as input (no dedicated input)