CSE598A/EE597G Spring 2006. Phase Locked Loop Design. KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering. Frequency Synthesizer. General Synthesizer Issues. Frequency Spectrum. Settling Time (Lock Time). PLL Components Circuits. PLL Components Circuits.
Phase Locked Loop
KyoungTae Kang, Kyusun Choi
Computer Science and Engineering
B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998
Park, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group
J. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,”Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.Charge Pumps
Chan-Hong Park, Solid-State Circuits, 1999.
Negative Skewed Delay Scheme:
Seog-Jun, Lee, ISSC, 1997
Yalcin Alper Eken, Solid-State Circuits, 2004