CSE598A/EE597G   Spring 2006
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CSE598A/EE597G Spring 2006. Phase Locked Loop Design. KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering. Frequency Synthesizer. General Synthesizer Issues. Frequency Spectrum. Settling Time (Lock Time). PLL Components Circuits. PLL Components Circuits.

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Phase Locked Loop Design

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Phase locked loop design

CSE598A/EE597G Spring 2006

Phase Locked Loop

Design

KyoungTae Kang, Kyusun Choi

Electrical Engineering

Computer Science and Engineering


Frequency synthesizer

Frequency Synthesizer


General synthesizer issues

General Synthesizer Issues


Frequency spectrum

Frequency Spectrum


Settling time lock time

Settling Time (Lock Time)


Pll components circuits

PLL Components Circuits


Pll components circuits1

PLL Components Circuits


Reference circuit

Reference Circuit


Pll components circuits2

PLL Components Circuits


Pfd and charge pump

PFD and Charge Pump

Spur!!


Phase frequency detector 1

Phase Frequency Detector(1)


Phase frequency detector 2

Phase Frequency Detector(2)


Pfd and modified flip flop

PFD and modified flip-flop

B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998

Park, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group


New modified flip flop by kt

New Modified flip-flop by KT

  • Reduce signal path

  • High speed

  • 10 Transistors

  • Negative reset

  • No oscillation

  • Customized


D flip flop

D Flip-Flop


Dff simulation comparison

DFF Simulation Comparison

  • Modifed FF by KT

  • DFF


Pfd simulation 1

PFD Simulation(1)


Pfd simulation 2

PFD Simulation(2)


Pfd simulation 3

PFD Simulation(3)


Pfd output stage charge pump

PFD Output Stage-Charge Pump

Programmable


Charge pump drain s w

Charge Pump (Drain–s/w)

  • My first Charge pump.

  • Easy to design and understand how to work

  • Spike Noise from net76 when U2 turn on

  • High noise contribution!

  • If you designed CP like this, you got fired!


Charge pump source s w

Charge Pump (Source-s/w)

  • Low charge sharing

  • Low noise

  • Suppression the Spur

Why? Cascode?

>High impedence

>Pole!!!

Level?


Charge pump simulation

Charge Pump Simulation

CP_Drain

CP_Source

V(U/D)

I(U)

I(D)


Charge pumps

Rhee, W., "Design of high performance CMOS charge pumps in phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

J. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,”Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.

Charge Pumps


Loop filter 1

Loop Filter(1)


Loop filter 2

Loop Filter(2)


Pll components circuits3

PLL Components Circuits


Differential delay cell single pass

Differential Delay Cell-Single pass

Chan-Hong Park, Solid-State Circuits, 1999.


Differential delay cell multiple pass

Differential Delay Cell-Multiple pass

Negative Skewed Delay Scheme:

Seog-Jun, Lee, ISSC, 1997

Yalcin Alper Eken, Solid-State Circuits, 2004


Single pass ring osc

Single pass Ring OSC.


Multiple pass ring osc

Multiple pass Ring OSC.

  • Which one is faster?

  • 3 stage single pass Ring OSC.

  • 5 stage multiple pass Ring OSC.


3 stage single pass ring osc

3 Stage-Single pass Ring OSC.

  • 220MHz~825MHz @ V(Ctrl)=1.65V~3.3V


3 stage single pass ring osc1

3 Stage-Single pass Ring OSC.


5 stage multiple pass ring osc

5 Stage-Multiple pass Ring OSC.

  • 1.65GHz~2.5GHz @ V(Ctrl) 1.65V~3.3V


How to simulate oscillator in hspice

.Option

Transient Step

Start-up time

Triggered Signal

Frequency Measure Tool: Cscope

How to simulate Oscillator in Hspice?


Pll components circuits4

PLL Components Circuits


Frequency divider

Frequency Divider

  • Input stage-high speed, low power, Following stages-High speed

  • Differential type-Suppression Noise

  • Input buffer is required


N 64 divider simulation

N=64 Divider Simulation


Input buffer

Input buffer


Pll simulation

PLL Simulation

V(VCO)

V(Ref)

V(DiV)

V(Up)

V(Dn)

V(Ctrl)


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