CSE598A/EE597G   Spring 2006
Download
1 / 40

Phase Locked Loop Design - PowerPoint PPT Presentation


  • 128 Views
  • Uploaded on

CSE598A/EE597G Spring 2006. Phase Locked Loop Design. KyoungTae Kang, Kyusun Choi Electrical Engineering Computer Science and Engineering. Frequency Synthesizer. General Synthesizer Issues. Frequency Spectrum. Settling Time (Lock Time). PLL Components Circuits. PLL Components Circuits.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' Phase Locked Loop Design' - xue


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

CSE598A/EE597G Spring 2006

Phase Locked Loop

Design

KyoungTae Kang, Kyusun Choi

Electrical Engineering

Computer Science and Engineering













Pfd and modified flip flop
PFD and modified flip-flop

B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998

Park, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group


New modified flip flop by kt
New Modified flip-flop by KT

  • Reduce signal path

  • High speed

  • 10 Transistors

  • Negative reset

  • No oscillation

  • Customized



Dff simulation comparison
DFF Simulation Comparison

  • Modifed FF by KT

  • DFF






Charge pump drain s w
Charge Pump (Drain–s/w)

  • My first Charge pump.

  • Easy to design and understand how to work

  • Spike Noise from net76 when U2 turn on

  • High noise contribution!

  • If you designed CP like this, you got fired!


Charge pump source s w
Charge Pump (Source-s/w)

  • Low charge sharing

  • Low noise

  • Suppression the Spur

Why? Cascode?

>High impedence

>Pole!!!

Level?


Charge pump simulation
Charge Pump Simulation

CP_Drain

CP_Source

V(U/D)

I(U)

I(D)


Charge pumps

Rhee, W., "Design of high performance CMOS charge pumps in phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

J. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,”Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.

Charge Pumps


Loop filter 1
Loop Filter(1) phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Loop filter 2
Loop Filter(2) phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Pll components circuits3
PLL Components Circuits phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Differential delay cell single pass
Differential Delay Cell-Single pass phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

Chan-Hong Park, Solid-State Circuits, 1999.


Differential delay cell multiple pass
Differential Delay Cell-Multiple pass phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

Negative Skewed Delay Scheme:

Seog-Jun, Lee, ISSC, 1997

Yalcin Alper Eken, Solid-State Circuits, 2004


Single pass ring osc
Single pass Ring OSC. phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Multiple pass ring osc
Multiple pass Ring OSC. phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

  • Which one is faster?

  • 3 stage single pass Ring OSC.

  • 5 stage multiple pass Ring OSC.


3 stage single pass ring osc
3 Stage-Single pass Ring OSC. phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

  • 220MHz~825MHz @ V(Ctrl)=1.65V~3.3V


3 stage single pass ring osc1
3 Stage-Single pass Ring OSC. phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


5 stage multiple pass ring osc
5 Stage-Multiple pass Ring OSC. phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

  • 1.65GHz~2.5GHz @ V(Ctrl) 1.65V~3.3V


How to simulate oscillator in hspice

.Option phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

Transient Step

Start-up time

Triggered Signal

Frequency Measure Tool: Cscope

How to simulate Oscillator in Hspice?


Pll components circuits4
PLL Components Circuits phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Frequency divider
Frequency Divider phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

  • Input stage-high speed, low power, Following stages-High speed

  • Differential type-Suppression Noise

  • Input buffer is required


N 64 divider simulation
N=64 Divider Simulation phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Input buffer
Input buffer phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548


Pll simulation
PLL Simulation phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp. 545-548

V(VCO)

V(Ref)

V(DiV)

V(Up)

V(Dn)

V(Ctrl)


ad