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A 0.13um CMOS Rad-hard proven technology with associated mixed mode circuit design approaches for space applications

A 0.13um CMOS Rad-hard proven technology with associated mixed mode circuit design approaches for space applications. Laurent Dugoujon (1), Constantin Papadas (2) and Bill Sinnis (2) 1) ST Microelectronics, 12 rue Jules Horowitz, B.P. 217, 38019 Grenoble Cedex, France

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A 0.13um CMOS Rad-hard proven technology with associated mixed mode circuit design approaches for space applications

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  1. A 0.13um CMOS Rad-hard proven technology with associated mixed mode circuit design approaches for space applications Laurent Dugoujon (1), Constantin Papadas (2) and Bill Sinnis (2) 1) ST Microelectronics, 12 rue Jules Horowitz, B.P. 217, 38019 Grenoble Cedex, France 2) Integrated Systems Development S.A., Atrina Center, Building B, 32 Kifisias Avenue, 15125 Marousi, Greece.

  2. INTRODUCTION • New Telecommunications Satellites must offer: • High data throughput • Uninterrupted Service • High Reliability • Competitive costs - The usage of Deep-Sub-Micron technology is now mandatory to keep-up with US manufacturers -

  3. KEY FUNCTIONS • Some functions are « key » to succes: • Broadband Analog-Digital Converters: ADC & DAC • High Speed Serial Links • Digital Processing ASICs - For these key components, only modern technology nodes (<=0.25um) can fulfill the specifications -

  4. TECHNOLOGY / FUNCTIONS

  5. RH at PROCESS LEVEL

  6. 0.13µm Technology Platforms Digital/Analog/RF convergence HCMOS9 Core Process 4 or 6 Cu Dual Damascene Metal levels 0.41µm pitch metallization, Low k dielectric HCMOS9DRAM 0. 39/ 0.53µm² HCMOS9i HCMOS9 A HCMOS9 SOI BICMOS9 HCMOS9 SiGe

  7. HCMOS9 : Device list CAPACITORS • 2 fF/µm² MIM capacitor (option) • N+Poly/NWell capacitor (GO2:50A) • P+Poly/PWell capacitor (GO2:50A) • Interdigited Metal fringe capacitor (MOM) • Intermetal capacitor (MEM) MOSFETs • 1.2V HS 0.13µm CMOS (GO1 : 20A) • 1.2V LL 0.13µm CMOS (GO1 : 20A) • 2.5V CMOS (GO2 : 50A) • 2.5V HS CMOS (GO2 : 50A) (option) • DRIFT N & P MOS transistors (GO2:50A) • NMOS SRAM (option) JUNCTION DIODES • N+/Pwell • P+ /Nwell RESISTORS • Silicided N+ Poly; 10 Ohm/sq • Unsilicided p+ Active; 135 Ohm/sq • Unsilicided P+ Poly; 320 Ohm/sq • Hipo; 1KOhm/sq (option) • Unsilicided N+ Poly; 110 Ohm/sq

  8. ST 130 & 90nm SRAMs are invulnerable to thermals 7Li Recoil Low Energy Neutron 104 0.84 MeV 103 10B Fission  - particle 102 1.47 MeV 101 Neutron Cross-section (barns) 100 Oxygen Boron-11 10-1 BORON 10 Tungsten Nitrogen Titanium Aluminum Copper Phosphorus Arsenic Silicon 10-2 10-3 • Thermal neutrons highly interact with Boron10 • Highest concentration of Bo10 in today’s IC : borophosphosilicate glass (BPSG) film : not used in ST technologies • Test on 130nm ST SRAMs at ILB, Paris : no SEU with a fluence >1011n/cm2 • Test on a 90nm SRAMs at TRIUMF, Vancouver : no SEU variations with & without Cadnium shielding

  9. TID characterizations for 130nm MOSFETs & (r)SRAMs • Linear transistors 130nm (thin oxide) @ 30 MradSi - Tests performed by CERN • Threshold voltage shift < 10 mV : negligible • Subthreshold swing variations : negligible • Transconductance degradation of less than 10% • Linear transistors 130nm (thick oxide) @ 30 MradSi - Tests performed by CERN • Threshold voltage shift < 35 mV : negligible • Transconductance degradation of less than 10% • Two 130nm 1Mb SRAMs, standard and rSRAM tested at BNL @ 1 MradSi : • No bit error detected for each memory cut at initial and after each exposure step (0, 100, 500 and 1000Krads(Si)) • Full functionality verified for the 2 cuts after being exposed to 1Mrad(Si). These experimental results confirm the strong robustness of ST 130nm MOSFETS, SRAM and robust SRAMs CERN test report : “specifications should be met in terms of radiation requirements WITHOUT using enclosed transistors (with obvious benefits)”

  10. Responses to HI of 130nm regular & robust rSRAMs Experiments performed at the BNL, NY, 01/2004 Std SRAM rSRAM ref. The rSRAM has both a lower LETth (x10) & X-section at sat. (/3) than the regular SRAM No SEL recorded up to 80 MeV/cm2.mg for all tested SRAMs

  11. RH at LIBRARY LEVEL

  12. NAND Gate Guardbands Standard RHBD: Library Level

  13. RHBD: Library Level • Or … • Trench capacitors • Drain degeneration by drain contact distance • Silicide protect • Salicide protect

  14. RHBD: Library Level Redundant Latch Layout Standard (6 xtors) Redundant (14 xtors)

  15. RHBD: Library Level Triple Voting Scheme

  16. RH at DESIGN LEVEL

  17. Error Code Correction (eg Hamming) RHBD: Architecture Level ECC

  18. rSRAM validation Testchip in 130 nm • Content : • SRAM Standard 1Mb • memcell 2.5 µm2 • SRAM Standard 1Mb • memcell 2.5 µm2 with Triple Well • rSRAM 1Mb • robust memcell 2.5 µm2 • rSRAM 1Mb • robust memcell 2.5 µm2 - ver. 2 (lower capacitor value) • 50x164Kb • robust memcell 2.5 µm2 • Package : • PBGA 27x27 276+16 1Mb SRAM 1Mb SRAM 1Mb rSRAM 1Mb rSRAM scribes • PLL, BIST, Laser Fuses Chip micrograph

  19. Relative perf between a standard, robust and ECC SRAM 130nm Single-Port SRAM - 32kx32 HCMOS9GP-LL, typical corner, 1V2, room temp. 90nm Single-Port SRAM - 8kx32 CMOS90-GP, typical corner, 1V, room temp. Note1 : pipeline architecture, Note2 : penalty induced by the additional parity bits (= +7 bits for a 32 bit-word ) and combinatonial logic (XOR stage) rSRAM offers lower die cost than ECC with a similar robustness

  20. Alpha & neutron responses of the 130nm rSRAM Experiments performed at Los Alamos and Crolles, 2003 Alpha accelerated results @ 1.2V Neutron accelerated results @ 1.2V ST rSRAM provides a robustness enhancement by ×250 : SER < 10 FIT/Mb @ 1.2 V + full immunity @ 1.32 V

  21. RHBD: Library Mapping (synthesis)

  22. LOGO TAP0 Sense amplifier PLL UWBTBA Robust Designs: PLL and Sense Amplifier PLL Technology: 0.13um Locking Frequency: 620MHz CtoC Jitter: 17ps Power Consumption: 340mW Sense Amplifier Technology: 0.13um Bandwidth: 4GHz Gain: 12db Power Consumption: 15mW

  23. Robust Designs: 64x1bit ADC 64x1bit-ADC Technology: 0.13um Sampling Frequency: 3GHz Power Consumption: 500mW

  24. Robust Designs: 10bit DAC 10bit-DAC Technology: 0.13um Topology: Current Steering Sampling Frequency: 15MHz Signal bandwidth~2.5MHz ENOB: 8.73bits Imax=1.4mA Noise: +/- 2LSB

  25. Robust Designs: 10bit ADC 10bit-ADC Technology: 0.13um Topology: Interleaved SAR Sampling Frequency: 1.3GHz Consumption: 400mW ENOB: in test Noise: in test

  26. CONCLUSION • It is the CONJUNCTION of 3 main levels of efforts which can maximize the Radiations performances: • Intrinsic good choices at Si process level (materials,...) • usage of validated mitigation techniques (libraries, options,...) • design for Rad-hard (architecture, registers,...) • We are able to manage all these levels with additional know-how from space industry trough contractual projects

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