CMOS SEQUENTIAL CIRCUIT DESIGN
Download
1 / 19

CMOS SEQUENTIAL CIRCUIT DESIGN - PowerPoint PPT Presentation


  • 129 Views
  • Uploaded on

CMOS SEQUENTIAL CIRCUIT DESIGN. Integrated Circuits Spring 2001 Dept. of ECE University of Seoul. Combinational vs. Sequential Logic.  Combinational Logic OUT(t)  IN(t).  Sequential Logic OUT(t)  IN(t)  IN(t-kT)  OUT(t-kT).  Positive Feedback  Charge on Cap.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' CMOS SEQUENTIAL CIRCUIT DESIGN' - harlow


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

CMOS SEQUENTIAL CIRCUIT DESIGN

Integrated Circuits

Spring 2001

Dept. of ECE

University of Seoul


Combinational vs sequential logic
Combinational vs. Sequential Logic

  •  Combinational Logic

  • OUT(t)  IN(t)

 Sequential Logic

OUT(t)  IN(t)

 IN(t-kT)

 OUT(t-kT)

 Positive Feedback

 Charge on Cap.


Sequential logic w positive feedback
Sequential Logic w/ Positive Feedback

  •  Two Inverters in Positive Feedback

  •  STATIC


Bi stability
Bi-stability

  •  Transition Region  Stable Regions

  •  Slope (Gain) >1


Sr latch

R

S

Q

Q

S

Q

0

Q

0

Q

S

Q

0

0

1

1

Q

R

0

1

0

1

Q

R

1

0

1

0

R

S

Q

Q

S

Q

S

Q

1

Q

1

Q

Q

R

0

1

1

0

Q

R

1

0

0

1

0

1

0

1

SR Latch

  •  NOR-Based

 NAND-Based


Jk flip flop

L

H

H

Q

L L

H

?

Q

H

H H

L

H

HL

L

L H

JK Flip-Flop

f=H




Master slave flip flop

H

L

L

L

H

H

L

H

Master/Slave Flip-Flop

  • master

slave

 One-Catching

 Level-Sensitive

Input Data Valid @ f=High




Flip flop timing constraints
Flip-Flop Timing Constraints

  •  Setup Time tsetup Hold Time thold

  •  Propagation Delay tpFF


Flip flop timing example
Flip-Flop Timing Example

  • T > tpFF + tp,comb + tsetup

f

Y

Q

FF’s

LOGIC

tp,comb



Pseudo static d latch
Pseudo-Static D-Latch

 f=High (Data I/O)  f=Low (Data Store)


M s d ff pseudo static
M/S D-FF (pseudo-Static)

  •  f=High  New Data In & Previous Data Store

 f=Low  New Data Out & New Data Store



M s d ff problem solution
M/S D-FF Problem Solution

Non-Overlapping 2-Phase Clocks



ad