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CMOS SEQUENTIAL CIRCUIT DESIGN

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CMOS SEQUENTIAL CIRCUIT DESIGN

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CMOS SEQUENTIAL CIRCUIT DESIGN

Integrated Circuits

Spring 2001

Dept. of ECE

University of Seoul

- Combinational Logic
- OUT(t) IN(t)

Sequential Logic

OUT(t) IN(t)

IN(t-kT)

OUT(t-kT)

Positive Feedback

Charge on Cap.

- Two Inverters in Positive Feedback
- STATIC

- Transition Region Stable Regions
- Slope (Gain) >1

R

S

Q

Q

S

Q

0

Q

0

Q

S

Q

0

0

1

1

Q

R

0

1

0

1

Q

R

1

0

1

0

R

S

Q

Q

S

Q

S

Q

1

Q

1

Q

Q

R

0

1

1

0

Q

R

1

0

0

1

0

1

0

1

- NOR-Based

NAND-Based

L

H

H

Q

L L

H

?

Q

H

H H

L

H

HL

L

L H

f=H

H

L

L

L

H

H

L

H

- master

slave

One-Catching

Level-Sensitive

Input Data Valid @ f=High

- Setup Time tsetup Hold Time thold
- Propagation Delay tpFF

- T > tpFF + tp,comb + tsetup

f

Y

Q

FF’s

LOGIC

tp,comb

f=High (Data I/O) f=Low (Data Store)

- f=High New Data In & Previous Data Store

f=Low New Data Out & New Data Store

Non-Overlapping 2-Phase Clocks