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FPGA families ( 2 )

ECE 448 Lecture 20. FPGA families ( 2 ). The Programmable Marketplace Q1 Calendar Year 2005. PLD Segment. FPGA Sub-Segment. Lattice. Xilinx. QuickLogic: 2%. Actel. Other: 2%. 7%. 5%. 58%. 33%. 51%. 31%. 11%. Xilinx. Altera. Altera. All Others.

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FPGA families ( 2 )

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  1. ECE 448 Lecture 20 FPGA families (2) ECE 448 – FPGA and ASIC Design with VHDL

  2. The Programmable MarketplaceQ1 Calendar Year 2005 PLD Segment FPGA Sub-Segment Lattice Xilinx QuickLogic: 2% Actel Other: 2% 7% 5% 58% 33% 51% 31% 11% Xilinx Altera Altera All Others Two dominant suppliers, indicating a maturing market Source: Company reports Latest information available; computed on a 4-quarter rolling basis ECE 448 – FPGA and ASIC Design with VHDL

  3. PLD Market Share 17% 18% 20% 24% 28% 32% 39% $2.1B $2.6B $4.1B $2.6B $2.3B $2.6B $3.1B 100% 32% 31% 33% 32% 32% 34% 31% 80% 60% Market Share (%) 40% 51% 50% 49% 44% 38% 35% 20% 30% 0% Calendar year 1998 1999 2000 2001 2002 2003 2004 Xilinx Altera All Others Source: Gartner Dataquest ECE 448 – FPGA and ASIC Design with VHDL

  4. A Maturing Market • Dominated by two players, Xilinx and Altera • With 51% and 32% share = 83% combined • Remaining players scramble for niches • All non-dedicated players have given up: • Intel, T.I., Motorola, NSC, AMD, Cypress, Philips… • Late-comers have been absorbed or failed: • Dynachip, PlusLogic, Triscend, SiliconSpice (absorbed) Chameleon, Quicksilver, Morphics, Adaptive Silicon (failed) The pace of innovation is set by the leaders ECE 448 – FPGA and ASIC Design with VHDL

  5. Rapidly Rising Cost of IC Design… 26 Prototype 24 22 20 Validation 18 16 14 Physical Cost ($M) 12 10 8 Verification 6 4 2 Architecture 0 Feature 0.35µm 0.25µm 0.18µm 0.13µm 90nm Dimension (80M) (2M) (40M) (5M) (20M) (Transistor Count) …makes most ASIC solutions too expensive Source: IBS: MS-FSA3.35 ECE 448 – FPGA and ASIC Design with VHDL

  6. Mainstream Requirements • Versatility, high performance, and low cost • Popular sub-functions @ ASIC performance and cost • User-friendly and capable tools • Many available cores, helpful tech support • Easy (partial) re-programmability • Signal integrity on the pc-board • Compatible I/O levels and standards • Many size, speed, temp and package options • Small-quantity part availability for fast prototyping ECE 448 – FPGA and ASIC Design with VHDL

  7. Low-Priority Niches • Single-chip, non-volatile, instant-on • is left to CPLDs, usually only for small systems • One-Time Programmable (OTP) • antifuse technology, limited appeal for aerospace • Ultra-low power for battery operation • conflicts with high performance (high leakage current) • Limited security, without using encryption • Antifuses and Flash are not meant for serious protection …of marginal interest to the main players ECE 448 – FPGA and ASIC Design with VHDL

  8. Unlimited Growth Opportunitiesin a $41 Billion Market Embedded Processing $3B Very High Performance DSP $3B ASSPs $15B PLD Market $5B ASICs $15B Market Data Source: Forward Concepts, Gartner Dataquest Forecast Database (May’05), iSuppli Forecast Database (Mar’05); 2008 Projection ECE 448 – FPGA and ASIC Design with VHDL

  9. Fab-Less is a Winner… • FPGAs require leading-edge technology to overcome inefficiencies relative to ASICs and ASSPs in transistor count, delay, extra I/O flexibility • Leading-edge fabs are expensive ($2B to $3B) • and become obsolete in a few years • Fabs like TSMC and UMC are very profitable pioneering aggressive technology, spreading the risk • FPGA companies do R&D, design, test, and marketing Provides stability, fast boom-time growth, and survival in a recession ! ECE 448 – FPGA and ASIC Design with VHDL

  10. Four Pillars of Progress • IC technology 90…65…45 nm • lower defect density, less leakage current • Chip architecture and CMOS circuitry • Software and Intellectual Property • cores • Innovative systems design / Applications • Massive parallelism in DSP, etc Much more than just “Moore’s Law” ECE 448 – FPGA and ASIC Design with VHDL

  11. IC Technology • 90 nm today, 65 nm 2006, 45 nm later • Moore’s Law is still alive for years to come • Low defect density achieves high yield, low cost • 3.3-V compatibility and tolerance are getting problematic • Thick oxide for I/O, thin oxide for logic fabric • Thin oxide increases performance, but also leakage • Mediumoxide ideal for config. cells, pass transistors Reducing leakage current is a major goal ECE 448 – FPGA and ASIC Design with VHDL

  12. FPGA families • Low-cost High-performance Spartan 3 Virtex 4 LX / SX / FX Spartan 3E Xilinx Cyclone II Stratix II Stratix II GX Altera ECE 448 – FPGA and ASIC Design with VHDL

  13. Architecture of low-cost Altera FPGAs: Cyclone II ECE 448 – FPGA and ASIC Design with VHDL

  14. ECE 448 – FPGA and ASIC Design with VHDL

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  19. Spartan-3 FPGA Family Members ECE 448 – FPGA and ASIC Design with VHDL

  20. ECE 448 – FPGA and ASIC Design with VHDL

  21. DLL vs PLL DLL is a rugged & reliable digital circuit PLL is a more sensitive linear circuit Voltage-controlled Oscillator needs clean supply DLL has unavoidable jitter PLL can reduce jitter, But only if carefully designed and supplied Frequency Multiplication is easier with PLL PLL supply filtering can be very difficult ECE 448 – FPGA and ASIC Design with VHDL

  22. ECE 448 – FPGA and ASIC Design with VHDL

  23. ECE 448 – FPGA and ASIC Design with VHDL

  24. Spartan-3 Block RAM Amounts ECE 448 – FPGA and ASIC Design with VHDL

  25. Block RAM Port Aspect Ratios ECE 448 – FPGA and ASIC Design with VHDL

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  29. Xilinx Spartan 3 Basic I/O Block Structure Q D Three-State EC FF Enable Three-StateControl Clock SR Set/Reset Q D Output EC FF Enable Output Path SR Direct Input FF Enable Input Path Q D Registered Input EC SR ECE 448 – FPGA and ASIC Design with VHDL

  30. Architecture of high-performance Altera FPGAs: Stratix II ECE 448 – FPGA and ASIC Design with VHDL

  31. ECE 448 – FPGA and ASIC Design with VHDL

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  36. ECE 448 – FPGA and ASIC Design with VHDL

  37. ECE 448 – FPGA and ASIC Design with VHDL

  38. ECE 448 – FPGA and ASIC Design with VHDL

  39. ECE 448 – FPGA and ASIC Design with VHDL

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  41. ECE 448 – FPGA and ASIC Design with VHDL

  42. ECE 448 – FPGA and ASIC Design with VHDL

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  44. ECE 448 – FPGA and ASIC Design with VHDL

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  47. ECE 448 – FPGA and ASIC Design with VHDL

  48. Architecture of high-performance Altera FPGAs: Stratix II GX ECE 448 – FPGA and ASIC Design with VHDL

  49. ECE 448 – FPGA and ASIC Design with VHDL

  50. ECE 448 – FPGA and ASIC Design with VHDL

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