n xyter engineering run preparations introductory to hans kristian soltveit s report
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n-XYTER Engineering Run Preparations, Introductory to Hans Kristian Soltveit´s report. Christian J. Schmidt. 14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009. Data Driven Front-End: Asynchronous Channel Trigger. detection of statistical, poisson distributed signals.

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n xyter engineering run preparations introductory to hans kristian soltveit s report

n-XYTER Engineering RunPreparations, Introductory to Hans Kristian Soltveit´s report

Christian J. Schmidt

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

data driven front end asynchronous channel trigger
Data Driven Front-End: Asynchronous Channel Trigger

detection of statistical, poisson distributed signals

triggertimestamp reg.

comparator

Time WalkCompensationcircuit

FASTshaper 18.5 ns

peaking

PDH

reset

chargepreamp

dig. FIFO

chargeinput

SLOW shaper(2 stages)

140 ns peaking time

Peakdetector &

hold,

free running

pulse height

output

analogue FIFO

Asynchronous registry and storage in 4-level fifo guarantees data loss < 4 %

when read-out through token ring

The DETNI ASIC 1.0, a front-end evaluation chip in AMS 0.35µ

analogue signal sequence test channel
Analogue Signal Sequence (Test Channel)

Testpulse Release

Slow Shaper

Fast Shaper

Discriminator Output

some in channel discriminator feedback detected
Some In-Channel Discriminator Feedback Detected

...upon removal of discriminator-power decouppling

correlates with trigger

These issues are particularly important with the self triggered architecture!

They will be addressed even more in the next engineering run.

channel layout overview clock domains and power
Channel layout overview, Clock Domains and Power

time stampfast clock

analogue domain

no clock

digital domain

system clock

total of 4 nF

on chip MIM caps

memory control ( 9 bit )

PDH reset

comp

analogue front end , PDH

comp – TWCtrim reg

analoguemem.

maskreg.

mono

synch

control

tokencell

ch.ID

digitalmem.

TSlatch

clocktree

PAD

A/Dguard ring

input MOSGND

digitalBULK

analogueGND& BULK

analogueVDD

comparatorVDD

digitalGND

digitalVDD

8 mm

5 mm

current status
Current Status
  • First batch of 250 chips has been extensively worked on:
    • n-XYTER has been integrated into the CBM DAQ chain
    • it was employed in the CBM test beam activities and
    • extensively tested
  • Engineering run in preparation with the aim to
    • Supply enough data driven readout chips for FAIR detector prototyping
    • Identify and correct the source for the enormous temp. coefficient
    • Improve layout related signal cross talk on the chip
    • Employ production process with no epilayer (
  • 110 000 Euros available for the engineering run (6000 chips), order is already out
  • Submission of the robust n-XYTER Nov/Dec this year.
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