Ece 545 digital system design with vhdl lecture 1
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ECE 545—Digital System Design with VHDL Lecture 1. Digital Logic Refresher Part B – Sequential Logic Building Blocks. Lecture Roadmap – Sequential Logic. Sequential Logic Building Blocks Flip-Flops, Latches Registers, Shift Registers Counters RAM. Textbook References.

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ECE 545—Digital System Design with VHDL Lecture 1

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ECE 545—Digital System Design with VHDLLecture 1

Digital Logic Refresher

Part B – Sequential Logic Building Blocks


Lecture Roadmap – Sequential Logic

  • Sequential Logic Building Blocks

    • Flip-Flops, Latches

    • Registers, Shift Registers

    • Counters

    • RAM


Textbook References

  • Sequential Logic Review

    • Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd or 3rd Edition

      • Chapter 7 Flip-flops, Registers, Counters, and a Simple Processors

        (7.3-7.4, 7.8-7.11 only)

    • ORyour undergraduate digital logic textbook (chapters on sequential logic)


Sequential Logic Building Blocks

some slides modified from:Brown and Vranesic, “Fundamentals of Digital Logic with VHDL Design, 2nd Edition”S. Dandamudi, “Fundamentals of Computer Organization and Design”


Introduction to Sequential Logic

  • Output depends on the current input and the internal state

  • Past inputs effects the internal state

  • Sequential circuits consist typically of

    • Storage elements (flip-flop, latch, register, RAM, etc.)

    • Combinational logic


Introduction (cont’d)

Main components of a typical synchronous sequential circuit

(synchronous = uses a clock to keep circuits in lock step)

INPUT

COMBINATIONAL

LOGIC

OUTPUT

NEXT STATE

S(t+1)

PRESENT STATE

S(t)

STATE-HOLDING STORAGE ELEMENTS

(i.e. FLIP-FLOPS)

CLOCK


State-Holding Memory Elements

  • Latch versus Flip Flop

    • Latches are level-sensitive: whenever clock is high, latch is transparent

    • Flip-flops are edge-sensitive: data passes through (i.e. data is sampled) only on a rising (or falling) edge of the clock

    • Latches cheaper to implement than flip-flops

    • Flip-flops are easier to design with than latches

  • In this course, primarily use D flip-flops


D Latch vs. D Flip-Flop

D

D

Q

CLK

CLK

Q

Latch transparent when clock is high

D

CLK

D

Q

CLK

Q

“Samples” D on rising edge of clock


Q

D

Clock

D latch

Truth table

Graphical symbol

Q(t+1)

Clock

D

Q(t)

0

0

1

0

1

1

1

Timing diagram

t

t

t

t

1

2

3

4

Clock

D

Q

Time


Q

D

Clock

D flip-flop

Truth table

Graphical symbol

Q(t+1)

Clk

D

0

0

1

1

Q(t)

0

Q(t)

1

Timing diagram

t

t

t

t

1

2

3

4

Clock

D

Q

Time


Bubble on the symbol means “active-low”

When Set = 0, set Q to 1

When Set = 1, do nothing

When Reset = 0, set Q to 0

When Reset = 1, do nothing

“Set” and “Reset” also known as “Preset” and “Clear” respectively

In this circuit, Set and Reset are asynchronous

Q changes immediately when preset or clear are active, regardless of clock

D Flip-Flop with Asynchronous Set and Reset

Set

Q

D

Q

Reset


D Flip-Flop with Synchronous Reset

  • Asynchronous active-low Reset: Q immediately clears to 0

  • Synchronous active-low Reset: Q clears to 0 on rising-edge of clock

D

Reset

CLK

Reset

Q(asynchronous Reset)

Q(synchronous Reset)


4

4

D

Q

Clock

Register

  • In typical nomenclature, a register is a name for a collection of flip-flops used to hold a bus

  • All flip-flops of a register share the same clock and control signals

D(3)

Q(3)

D

Q

CLK

D(2)

Q(2)

D

Q

CLK

D(1)

Q(1)

D

Q

CLK

D(0)

Q(0)

D

Q

CLK


Q

Q

Q

Q

3

2

1

0

Sin

Q

Q

Q

Q

Q

D

D

D

D

Clk

(a) Circuit

Q

Q

Q

Q

=

Q

Sin

3

2

1

0

t

1

0

0

0

0

0

t

0

1

0

0

0

1

t

1

0

1

0

0

2

t

1

1

0

1

0

3

t

1

1

1

0

1

4

t

0

1

1

1

0

5

t

0

0

1

1

1

6

t

0

0

0

1

1

7

Shift Register

SHIFTREGISTER

Clk

Sin

Q


4

4

4

4

Enable

Enable

D

D

Q

Q

Load

Sin

Sin

Clock

Clock

4-bit Shift Registers: symbols

a) with Enable

b) with Enable and Parallel Load


D

D

D

D

Q

Q

Q

Q

Shift Register with Enable: internal structure

Q(1)

Q(0)

Q(2)

Q(3)

Sin

Clock

Enable


D(0)

D

D

D

D

Q

Q

Q

Q

Shift Register with Parallel Load: internal structure

Load

D(3)

D(1)

D(2)

Sin

Clock

Enable

Q(3)

Q(2)

Q(1)

Q(0)


Synchronous Up Counter

  • Enable (synchronous): when high enables the counter, when low counter holds its value

  • Load (synchronous) : when load = 1, load the desired value into the counter

  • Output carry: indicates when the counter “rolls over”

  • D3 downto D0, Q3 downto Q0 is how to interpret MSB to LSB

enable

load

carry

D0

Q0

D1

Q1

D2

Q2

D3

Q3

clock


Random Access Memory (RAM)

  • More efficient than registers for storing large amounts of data

  • Can read and write to RAM

  • Addressable memory

  • RAM dimensions are:

    • (number of words) x (bits per word)

  • Address is m bits, data is n bits

    • 2m x n-bit RAM

  • Example: address is 5 bits, data is 8 bits

    • 32 x 8 RAM

  • Write Enable (WE)

    • When set, writing takes place

      at the next rising edge of

      the clock

RAM

DIN

DOUT

n

n

ADDR

m

WE

CLK


Dual-Port RAM

  • Two sets of input ports

    {DINA, ADDRA, WEA}

    {DINB, ADDRB, WEB}

  • Two corresponding outputs

    DOUTA

    DOUTB

  • One memory matrix

  • Possible operations:

    • Read from two memory locations

    • Write to two different memory locations

    • Read from a memory location

      and write to a memory location

      (different or the same)

RAM

DINA

DOUTA

n

n

ADDRA

m

WEA

DINB

DOUTB

n

n

ADDRB

m

WEB

CLK


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