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# ECE 331 – Digital System Design - PowerPoint PPT Presentation

ECE 331 – Digital System Design. Logic Circuit Design (Lecture #7). Design Concepts. Combinational Logic Circuits Outputs are functions of (present) inputs No memory Can be described using Boolean expressions Hierarchical design Used to solve large design problems

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Logic Circuit Design

(Lecture #7)

Design Concepts

Combinational Logic Circuits

Outputs are functions of (present) inputs

No memory

Can be described using Boolean expressions

Hierarchical design

Used to solve large design problems

Break problem into smaller (sub-)problems

Solve each sub-problem (i.e. realize design)

Combine individual solutions

Design Concepts

Specification

Describes the problem to be solved.

Describes what needs to be done,

not how to do it.

Implementation

Describes how the problem is solved.

Design Concepts

Issues

Most solutions are not unique.

More than one solution may meet the specifications.

Cannot always satisfy all of the requirements.

Must identify (and study) design tradeoffs.

Cost

Speed

Power consumption

etc.

Design Process

Identify requirements (i.e. circuit specifications)

Determine the inputs and outputs.

Derive the Truth Table

Determine simplified Boolean expression(s)

Implement solution

Verify solution

Exercise:

Design a combinational logic circuit to meet the following specifications:

1. 3-bit input (A = a2a1a0)

2. 1-bit output (z)

3. Output is high (logic 1) when 2 < A <= 5.

Example:

Design a 7-Segment Decoder

1. Circuit Specification

The 7-Segment Decoder must decode Binary Coded Decimal (BCD) digits so that they can be displayed on a 7-Segment Display.

7-Segment Decoder

2. Determine Inputs and Outputs

Input: Binary Coded Decimal digits

7-Segment Decoder

Binary Coded Decimal

Assign a 4-bit code to each decimal digit.

A 4-bit code can represent 16 values.

There are only 10 digits in the decimal number system.

Unassigned codes are not used.

How do we interpret these unused codes?

Hint: think about K-maps.

BCD Digits

2. Determine Inputs and Outputs

Output: 7-Segment Display

7-Segment Decoder

7-Segment Display

7-Segment Display

3. Derive Truth Table

7-Segment Decoder

7-Segment Decoder

4. Determine simplified Boolean expression(s)

7-Segment Decoder

7-Segment Decoder

A

y

z

w

x

00

01

11

10

00

1

0

1

1

01

0

1

1

1

11

d

d

d

d

10

1

1

d

d

A = ?

7-Segment Decoder

B

y

z

w

x

00

01

11

10

00

1

1

1

1

01

1

0

1

0

11

d

d

d

d

10

1

1

d

d

B = ?

Student Exercise:

Determine the minimized Boolean expression for each of the segments of the 7-Segment Display.

7-Segment Decoder

5. Implement Solution

6. Verify Solution

7-Segment Decoder

Multiple-Output Logic Circuits

Example:

Given two functions, F1 and F2, of the same input variables x1.. x4, design the minimum-cost implementation.

Multiple-Output Logic Circuits

Multiple-Output Logic Circuits

x

x

x

x

1

2

1

2

x

x

x

x

3

4

3

4

00

01

11

10

00

01

11

10

00

1

1

00

1

1

01

1

1

1

01

1

1

11

1

1

11

1

1

1

10

1

1

10

1

1

(a) Function

f

(b) Function

f

1

2

F1 = X1'.X3 + X1.X3' + X2.X3'.X4

F1 = X1'.X3 + X1.X3' + X2.X3.X4

Multiple-Output Logic Circuits

x

2

x

3

x

4

f

1

x

1

x

3

x

1

x

3

f

2

x

2

x

3

x

4

f

f

(c) Combined circuit for

and

1

2

Example:

Given two functions, F3 and F4, of the same input variables x1.. x4, design the minimum-cost implementation for the combined circuit.

Multiple-Output Logic Circuits

Note: the minimum-cost implementation for the combined circuit may not

be the same as the minimum-cost implementations for the individual circuits.

Multiple-Output Logic Circuits

x

x

x

x

1

2

1

2

x

x

x

x

3

4

3

4

00

01

11

10

00

01

11

10

00

00

01

1

1

1

01

1

1

1

11

1

1

1

11

1

1

1

10

1

10

1

(a) Optimal realization of

(b) Optimal realization of

f

f

3

4

F3 = X1'.X4 + X2.X4 + X1'.X2.X3

F3 = X2'.X4 + X1.X4 + X1'.X2.X3.X4'

Logic Gates required:

2 2-input AND

1 3-input AND

1 3-input OR

Logic Gates required:

2 2-input AND

1 4-input AND

1 3-input OR

Total Gates and Inputs required:

8 Logic Gates

21 Inputs

Multiple-Output Logic Circuits

x

x

x

x

1

2

1

2

x

x

x

x

3

4

3

4

00

01

11

10

00

01

11

10

00

00

01

1

1

1

01

1

1

1

11

1

1

1

11

1

1

1

10

1

10

1

(c) Optimal realization of

f

and

f

together

3

4

F3 = X1'.X4 + X1.X2.X4 + X1'.X2.X3.X4'

F3 = X2'.X4 + X1.X2.X4 + X1'.X2.X3.X4'

Logic Gates required:

1 2-input AND

1 3-input AND

1 4-input AND

1 3-input OR

Logic Gates required:

1 2-input AND

1 3-input AND

1 4-input AND

1 3-input OR

shared logic gates

Total Gates and Inputs required:

6 Logic Gates

17 Inputs

Multiple-Output Logic Circuit

x

1

x

4

x

f

1

3

x

2

x

4

x

1

x

2

x

3

x

f

4

4

x

2

x

4

f

f

(d) Combined circuit for

and

3

4