digital design WITH vhdl Exercise 1

1. digital design WITH vhdlExercise 1 Muhammad Amir Yousaf

2. What is VHDL? What it is used for? Muhammad Amir Yousaf

3. VHDL vs Programming languages? Muhammad Amir Yousaf

4. VHDL • Very High Speed Integrated Circuit Hardware description Language: • Origininallydesigned to describe and specify hardware. • Specificationsweremadeexecutable with simulators. • Synthesizer weredeveloped to synthesize. Muhammad Amir Yousaf

5. VHDL - Modularity • Component in VHDL is refferd as ’entity’ and has a clear interface. Inputs Outputs Type and size. • Internal of component is calledarchitecturedeclaration. Complexity is hiddeninside. Made of components and wires. How the external world wouldsee it. Muhammad Amir Yousaf

6. Description of a digital component. • A component is to be designed with followingdescription: • A full adder that addstwo 1 bit inputs and a carry-in bit. The result is shown at a 1 bit SUM and a carry-out bit. Describe this component in (a standard descriptivelanguage) VHDL SUM Full Adder A B CIN COUT Muhammad Amir Yousaf

7. Description of a FULLadder with VHDL SUM Full Adder A B CIN COUT Muhammad Amir Yousaf

8. Description of a digital component. • A component is to be designed with followingdescription: • A full adder that addstwo 1 bit inputs and a carry-in bit. The result is shown at a 1 bit SUM and a carry-out bit. RST Let add a ‘RESET’ pin in the component. SUM Full Adder Describe this component in (a standard descriptivelanguage) VHDL A B CIN COUT Muhammad Amir Yousaf

9. Description of a digital component. • VHDL code: • If RST = ’1’ then • SUM <= ‘0’; • COUT <= ‘0’; • else • ------- • ------ • End if; • Ifis sequential, so must be contained in process. • Sequential or procedural statements execute in the order as they appear in code. • label: process (<senstivity_list>) Muhammad Amir Yousaf

10. Description of a FULLadder RST SUM Full Adder A B CIN COUT Muhammad Amir Yousaf

11. eXERCISES • Ex 1: Describe a system in VHDL with an input x and output y of type integer. The system gives x+10 at output whenever a change is detected on input. Ex 2: ´Describe a 4-bit comparator in VHDL using relational operators i.e > < =. gt 4 4 comp x eq lt y Ex 3: A MUX is described in VHDL as . MUX Make a 4-to-1 MUX using the structure of 2-to-1 MUXs. Muhammad Amir Yousaf

12. A model of a digital system is described • Is it time to translate it in hardware? Can wesimulate the results? Is it poosible to see and analyze the system performance? Muhammad Amir Yousaf

13. Simulatingdescription of digital design • A digital component is modeled in VHDL but not proven yet. • Model a ’TESTBENCH’ in VHDL to prove the performance of designed part. • ’TESTBENCH’ applies stimulus to the design and simulates the response of system. In stimulus weassign inputs to the system. Muhammad Amir Yousaf

14. TESTBENCH RST RST TESTBENCH SUM SUM Full Adder Full Adder A A Display Stimulus B B CIN COUT COUT CIN Muhammad Amir Yousaf

15. Testbench by xilinx Muhammad Amir Yousaf

16. Testbench by xilinx Muhammad Amir Yousaf

17. pRACTICAL • Letwemodel this in VHDL with xilinx Start Xilinx Muhammad Amir Yousaf

18. synthesize • Let translate our model into hardware • User IOs • 8 slide switches. • 8 LEDs • 4 push buttons • 4 seven segment displays RST SUM Full Adder A Digilent Nexys2 B CIN COUT Muhammad Amir Yousaf

19. synthesize • User IOs • 8 slide switches. • 8 LEDs • 4 push buttons • 4 seven segment displays • FPGA • .ucffile gives connection map • Top VHDL file • Gives top interface of the system. • Use Adept from Digilent to load the bit file in FPGA. Muhammad Amir Yousaf

20. Home Exercise: • VGA: • Read about VGA controller to know that how it works. • VGA reference document and VHDL code is given at: • http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,789&Prod=NEXYS2 Muhammad Amir Yousaf