HFT PIXEL Detector

1. HFT PIXEL Detector Director’s review 11-13 May-2009 Wieman

2. PIXEL Work • Eric Anderssen • Mario Cepeda • Leo Greiner • Tom Johnson • Howard Matis • Hans Georg Ritter • Thorsten Stezelberger • Xiangming Sun • Michal Szelezniak • Jim Thomas • Chi Vu ARES Corporation: Darrell Bultman Steve Ney Ralph Ricketts Erik Swensen

3. HFT inner tracker for STARto Extract D mesons from heavy ion collisons reduced combinatoric background with a precision vertex detector • special requirements: • low pt • high track density • must be extra thin with • excellent position resolution invariant mass

4. HFT precision inner tracker for STAR PIXELS • Inner tracking layers • SSD • IST • PIXELS • PIXELS – LBL project • PIXELS new technology • Ultra low X0, 50 m Silicon • monolithic silicon pixel chips • air cooling • rapid replacement, multiple detector copies • pre spatially calibrated 20 cm Inner layer 2.5 cm radius Outer layer 8 cm radius  coverage +-1 One of two half cylinders total 40 ladders

5. Topics • Features of the PIXEL detector • Development of active pixel silicon detector chips • Progress on read out and testing • Mechanical design, analysis, prototyping and testing

6. Some pixel features and specifications critical and difficult more than a factor of 2 better than other vertex detectors (ATLAS, ALICE and PHENIX)

7. Monolithic Active Pixel Sensors MAPS pixel cross-section (not to scale)‏ Detector chips developed by Marc Winter’s group at IPHC in Strasbourg, France • Standard commercial CMOS technology • Only NMOS transistors inside the pixels • Room temperature operation • Sensor and signal processing are integrated in the same silicon wafer • Signal is created in the low-doped epitaxial layer (typically ~10-15 μm) → MIP signal is limited to <1000 electrons • Charge collection is mainly through thermal diffusion (~100 ns), reflective boundaries at p-well and substrate → cluster size is about ~10 pixels (20-30 μm pitch)‏ • 100% fill-factor • Fast readout • Proven thinning to 50 micron

8. HFT PIXEL MAPS 120 GeV π- beam test at CERN M.i.p. detection performances of a 100 μs read-out CMOS pixel sensor with digitised outputs – Marc Winter et. al., http://arxiv.org/PS_cache/arxiv/pdf/0902/0902.2717v1.pdf CMOS pixel sensor development: a fast readout architecture with integrated zero Suppression – C. Hu, PIXEL 2008 Efficiency and Fake hit rate for Mimosa-22. This sensor has the same design as the final HFT Pixel sensor. This sensor has been tested to 150k rad and maintained 99.5% efficiency with < 10-4 fake hit rate. Efficiency and Fake hit rate for Mimosa-16. 25um pixels at 20º C. This is the sensor design that is the basis for the HFT Phase-1 Pixel sensors.

9. Sensor development program Gen Sensor CHIPS designed by IPHC and tested at LBNL Mimostar–2 30 µm pixel, 128 x 128 array 3 layer telescope tested in STAR Mimostar–3 30 µm pixel, 320 x 640 array ½ size chip – production demonstration Phase–1 30 µm pixel, 640 x 640 array digital output full size chip - currently being tested at LBNL Final (Ultimate) 18.4 µm pixel, 1024 x 1088 array ≤ 200 µs integration time zero suppression 2 digital outputs (hit addresses only) 1 1 Will be used in engineering run (full system) 2 Final pixel detector 3

10. Sensor Development Status Final (Ultimate) – full reticle final sensor 1088 x 1024 pixels, 18.4 µm pitch, 150 MHz RDO clock, column level discriminators, zero suppression circuitry, 2 outputs for address data, <200 µs integration time. + Phase-1 SUZE – Zero suppression (prototype successfully tested 04/2008) The overall design is in progress. IHPC has produced a smaller prototype of the final STAR pixel sensor named Mimosa-26. It is currently under test in Strasbourg. Expected delivery of the final sensor prototype is early 2010.

11. LVDS Data Path Testing http://rnc.lbl.gov/hft/hardware/docs/LVDS/LVDS_test_report_1.pdf • Significant test of system data path at up to 200 MHz with 3 streams of pseudo-random data • Xilinx Virtex-5 IODELAY element allows fine tuning of all individual input latching in 75 ps increments. Only system jitter affects data latching. • Measured BER (bit error rate) of <10-14 for 1 m 42 AWG and 6 m twisted pair data cables at 200 MHz and for 2.3 m 42 AWG at 160 MHz. Ladder mock-up with 1-to-4 LVDS fanout buffers 42 AWG wires Mass termination board + LU monitoring 24 AWG wires 2 ns eye pattern opening for 1 m 42 AWG cables at 200 MHz Virtex-5 based RDO system with RORC link to PC

12. HFT PIXEL mechanical development

13. r1 r2 perceived vertex true vertex m x x v v r1 r2 perceived vertex true vertex vertex projection from two points expectations for the HFT pixels pointing resolution = (13  22GeV/pc) m first pixel layer from coulomb scattering from detector position error more than 3 times better than anyone else detector layer 2 detector layer 1

14. Mechanical Stability Once the pixel positions are measured will they stay in the same place to within 20 µm? Issues that must be addressed: • Movement from temperature changes • Movement from humidity changes • Deflection from gravity • Vibration movement from mounts in STAR • Movement induced by cooling air • how much air is required • vibration and static displacement

15. Stability requirement drives design choices • The detector ladders are thinned silicon, on a flex kapton/aluminum cable • The large CTE difference between silicon and kapton is a potential source of thermal induced deformation even with modest 10-15 deg C temperature swings • Two methods of control • ALICE style carbon composite sector support beam with large moment of inertia • Soft decoupling adhesive bonding ladder layers

16. FEA analysis of thermally induced deformation of sector beam • FEA shell elements • Shear force load from ladders • 20 deg temperature rise • Soft adhesive coupling • 200 micron carbon composite beam • end cap reinforcement • Maximum deformation 9 microns (30 microns if no end cap)

17. FEA analysis - sector beam deformation – gravity load • FEA shell analysis • 120 micron wall thickness composite beam • gravity load includes ladders • maximum structure deformation 4 microns • ladder deformation only 0.6 microns

18. Air cooling of silicon detectors – Computational Fluid Dynamics (CFD) analysis • Silicon power: 100 mW/cm2 (~ power of sunlight) • 240 W total Si + drivers air flow path – flows along both inside and outside surface of the sector

19. Air cooling – CFD analysis stream lines with velocity • air flow velocity 9-10 m/s • maximum temperature rise above ambient: 12 deg C • sector beam surface – important component to cooling • dynamic pressure force 1.7 times gravity silicon surface temperature velocity contours

20. wind tunnel setup to test vibration and displacement carbon fiber sector beam capacitance vibration probe two positions shown air in air out adjustable wall for air turn around air velocity probe two positions shown C:\Documents and Settings\Howard Wieman\My Documents\aps project\mechanical\PXL phase 1 sept 2008\sector ph1 wind tunnel.SLDASM

21. wind tunnel, rapid prototype parts from model air flow control parts built with 3D printer parts built with SLA, stereolithography apparatus

22. Ladder vibration induced by cooling air no reinforcement at the end system resolution limit all errors desired vibration target required air velocity 18 mph

23. 4 µm 6 µm 6 µm 3 µm 3 µm 13 µm 14 µm 2 µm 14 µm 8 µm 4 µm 11 µm measured vibration (RMS) induced by 9 m/s air flow open end reinforced end

24. prototype design being built

25. Eric Anderssen and Tom Johnson have been working on fabrication methods for: Sector Beam and Ladders Produced sample beams, 244 m thick, 7 ply, 21 gm expected ladder mass 7.5 gm Development of sector beam and ladder fabrication ladders sector beam

26. Sector structures

27. ladder fabrication and tooling finalizing mechanical designs and developing rapid production methods

28. Full sized cooling tests 9 inch diameter tube mocks up ISC Thermal camera window not shown > 300 CFPM air flow for verification of cooling capability Cooling tests will begin as soon as prototype sectors completed

29. conclusion • significant progress • detector chip development • silicon readout and testing • mechanical design, analysis, prototyping and testing