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Physics & Astronomy HEP Electronics. TIMING AND JITTER. ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004. Martin Postranecky John Lane, Matthew Warren.
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Physics & AstronomyHEP Electronics TIMING AND JITTER ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 Martin PostraneckyJohn Lane, Matthew Warren ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
The BC clock is output to all BOC/ROD slots as differential PECL. Point-to-point balanced tracks of identical length on the backplane are used for all slots, providing a synchronised clock for all BOCs & RODs The 8x commands TTC(n) are all clocked out onto the backplane simultaneously This TTCCLKB is delayed by an adjustable delay ( 6 bits of 0.5nsec ), pre-set by a ROD SETUP DIL switch. This allows for adjustments of the Setup and Hold times of the TTC(n) commands at the RODs to be made TIMING ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
Output Signals Timing ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
Timing of TTC Signals ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
U412 U402 U412 8x F/F 8x F/F U44 U52 TIM3 Clock Flow BCCLKLED TTCrm/rq CLOCK40 PECL Drivers U57 U56 CLOCK40DES1 BCCLK1B TTCCLK1B 9x CLOCK40 U42 TTCCLK2L MCLK1 PCLKB U52 TTCCLK2B FPGA2 ENSACLK FPGA2 8x CLOCK40 CLOCK40DES2 BCCLK1B U58 CLK MUX 2 U42 NIMEXTCLK CLKINB2 ROD Setup EXTCLKLED U46 DL2 SW8 ECLEXTCLK U36 U33 EXTCLK EXTCLKB ECLEXTCLK2 U48 DL1 U51 U45 CLKINB1 DL1OUT SACLKB CLKIN1 DL2OUT ENINTCLK SACLKLED CLKIN2 U42 FPGA2 U38 CLK MUX 1 NIMCLKOUT CT(5:0) U44 FPGA2 ECLCLKOUT1 INT_CLK 80Mhz Osc. ECLCLKOUT2 U39 DL2OUTB CLK0 TTCout(0-7) TTC(7-0)A CLK00 U44 TTC(7-0)B U44 CLKINB4 TIM Setup U47 DL4 SW7 Trigger Window WD(5:0) FPGA2 TIMCLK1L FPGA1 WS(5:0) DL4OUT FPGA2 TIMCLK2L SW10 FPGA2 U50 SW9 U69 DL TIMCLK3L Size U62 DL U63 DL U61 DL TRIGCLK DL4OUTB MRMW/MP v2.0 11-05-04 Delay Setup Size Comp. ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
TIMING ON BACKPLANE Clock on Test Board in Slot 14 Trigger on Test Board in Slot 14 5.0nS/div SetUp Time ~12nS Hold Time ~ 12nS ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
TIMING ON BACKPLANE Clock on Test Board in Slot 21 Trigger on Test Board in Slot 21 5.0nS/div Setup Time ~10nS Hold Time ~ 14nS ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
JITTER ON BACKPLANE SA CLOCK on TEST BOARD in Slot 19 SA CLOCK on TEST BOARD in Slot 14 500ps/div Delay 10uS Max.Jitter ~ 600pS p-p ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
JITTER ON TIM Stand-Alone PCLKB output from TIM-3 Trigger not running 200nS/div Delay 10uS Jitter ~ 350pS ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
JITTER ON TIM Stand-Alone PCLKB output from TIM-3 All TTC(n) running 200nS/div Delay 10uS Jitter ~ 300pS ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky : TIMING & JITTER
