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ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004

Physics & Astronomy HEP Electronics. TIM HARDWARE. ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004. Martin Postranecky John Lane, Matthew Warren. COMPONENTS USED. 2x FPGAs used : FPGA-1 : Xilinx 2S200E-6FG456C FPGA-2 : Xilinx 2S600E-7FG456C 2x Xilinx PROMs 7x Delay Lines PDU-16

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ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004

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  1. Physics & AstronomyHEP Electronics TIM HARDWARE ATLAS SCT/Pixel TIM FDR/PRR 28 June 2004 Martin PostraneckyJohn Lane, Matthew Warren ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  2. COMPONENTS USED • 2x FPGAs used : FPGA-1 : Xilinx 2S200E-6FG456C FPGA-2 : Xilinx 2S600E-7FG456C • 2x Xilinx PROMs • 7x Delay Lines PDU-16 • 4x Clock drivers/mpxs • 15x TTL/PECL/ECL/NIM • 14x LV buffers • 38x various TTL • 2x DC/DC modules • 8x transistors • 38x LEDs • 626x passive comp. • 20x connectors • 80x pin headers ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  3. TIM-3A MODULE • 9U x 400 mm, single width, VME64x module • Standard VME slave interface with A24 / D16 or A32 / D16 access • A16-23 ( or A16-31) Base Address, or GA address TIM-3A Power : ~ 7A of +5V ~ 2A of +3V3 ( incl. +1V8 supply) < 1A of +12V } for -5V2 supply < 1A of -12V Total power ~ 120 W ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  4. TIM Discretes vs FPGAs ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  5. TIM Functional Model ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  6. NIMEXTCLK 80.1573MHz XTAL Osc. ECLEXTCLK 2 EN 6x NIMEXTCOMMANDS 6 Internal Stand-Alone Commands MPX-PLL 6 4 6x 4x 6 6 4 6x ECLEXTCOMMANDS 6x EN 4x EN DELAY VME Commands 6 NIMEXTBUSY ECLEXTBUSY 6x 6 4x NIMDATAOUT CLOCK 4 6x 6x DATAOUT Sync 6 6x ECLDATAOUT CLOCK 6 TTC Interface CLK40DES1 TTCFIBRE TTCrx NIMCLKOUT 6x SACOMMANDS CLOCKOUT ECLCLKOUT 6 6x 6 SA BUSY 6x TTCCOMMANDS 6x EN 6 6x Sequencer 8x32K RAM 0-7 6 2x SEQID VME READ/WRITE 2 6x EN 2 2x FIFO ID COUNTERS 2x 2x 2 6x SEQCOMMANDS 2x EN VME ADDRESS BUS 2x EN 2 2 2x ID VME READ/WRITE 2x SERIALISER Sink 8x32K RAM 0-7 CLOCK VME READ 8x SINKDATA 6x DATAOUT CLOCKOUT DELAY CLOCK 6x SACOMMANDS 6x F/F MPX-PLL 6x TTCCOMMANDS TTCA(0-7) 6 6x SEQCOMMANDS 8x8 MAPPING DOUBLE 8x OUTPUTS TO P3 2x ID TTCB(0-7) 2 2x SEQID CLOCK 16x DIFFERENTIAL CLOCK OUTPUTS TO P3 16x RODBUSYMASK BUSY MODULE 16x RODBUSYOUT 16x RODBUSY INPUTS FROM P3 16 MP/(MRMW) v1.0 17-06-04 8x F/F 8x F/F ATLAS-SCT “TIM” Schematics ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  7. 1) INPUTS : From TTCrx interface module : CLOCK40DES1, TTC Fast Commands, ID Numbers From backplane : 16x ROD BUSY signals are received from individual RODs by PHILIPS N74LVT16244B LV Bus receivers. The active-low ROD BUSY lines are pulled up to +3V3 on the TIM, thus indicating empty ROD slots as NOT BUSY. 2) OUTPUTS : The 40MHz clock is distributed to all BOC cards as 16 individual differential PECL pairs via the J3 backplane. Driver chip is MOTOROLA MC100E111JC 1:9 PECL DIFFERENTIAL CLOCK DRIVER, which guarantee channel-to-channel skew to be below 50 ps. All on-board differential tracks, and all the P3 backplane tracks, are designed as point-to-point balanced 100R tracks of the same length ( ie. all the backplane slots receive clock with no time skew ) Each line of the differential pair has a 270R load resistor at the transmitter, and is terminated by 100R between the differential pair at the BOC receiver end. Eight active-low TTC(0-7) outputs are bussed to RODs on two separate backplane buses, each for 8x RODs. The devices chosen, PHILIPS N74ABT574D, are Advanced BiCMOS Bus Interface drivers, which guarantees VOL of below 0.55V while sinking 64mA, and VOH of above 2V while sourcing 32mA. With TIM is slot 13 in the middle of the crate, the TTC(0-7)A bus is terminated on the backplane in slot 21, and the TTC(0-7)B bus in slot 5. A) In the RUN MODE : ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  8. B) In the STAND-ALONE MODE : 1) INPUTS : From INTERNAl or EXTERNAL sources : • All Clock and Command Signals, including Busy, can be input as either NIM or differential ECL signals on the Front Panel • Same ECL external commands can also be input on the second half of this IDC dual connector. This allows one TIM to operate as a master & drive another TIM slave. At least four TIM slaves can be driven by one TIM master using a daisy-chain ribbon cable and removing the ECL differential termination on the first three modules 2) OUTPUTS : a) On backplane, same as in RUN MODE b) On Front Panel, additional interface outputs : The complete set of six TTC(0-5) type commands, together with BUSY and CLOCK, is output on one half of dual 16-pin IDC connector as 8x differential ECL pairs. C) SEQUENCER : Additionally, all 8x TTC-type commands can be input from the SEQUENCER RAM ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  9. TIM Backplane Interfaces ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  10. +5 +3 +12 VA TT TC RB LA ER FR -5 -12 OR VE SA SC TB CA BR SP -5V, -12V Power On +5V, +3.3V, +12V Power On Overall Reset VME Access 2 VME Error 1 TTC Mode (Run Mode) Stand-Alone Mode Stand-Alone Clock On TTC Clock On Overall ROD Busy 3 TIM Busy L1A signal issued CAL signal issued BCR signal issued ECR signal issued FER signal issued Spare signal issued ROD BUSY ROD Busy’s (1 per slot) 12 11 10 9 8 7 6 5 14 15 16 17 18 19 20 21 • NOTES: • VE Shows a VME bus error (flash) OR geog-addr error (i.e. wrong slot). • VA Flashes when TIM is accessed (addressed) by VME correctly. • RB In Stand-Alone Mode TIM is always busy. • All LEDs (apart from power supplies) have a 60ms pulse stretcher for better visibility. MRMW v1.0 15-05-04 TIM Front-Panel LEDs ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  11. TIM Front Panel Interfaces ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  12. U412 U402 U412 8x F/F 8x F/F U44 U52 TIM3 Clock Flow BCCLKLED TTCrm/rq CLOCK40 PECL Drivers U57 U56 CLOCK40DES1 BCCLK1B TTCCLK1B 9x CLOCK40 U42 TTCCLK2L MCLK1 PCLKB U52 TTCCLK2B FPGA2 ENSACLK FPGA2 8x CLOCK40 CLOCK40DES2 BCCLK1B U58 CLK MUX 2 U42 NIMEXTCLK CLKINB2 ROD Setup EXTCLKLED U46 DL2 SW8 ECLEXTCLK U36 U33 EXTCLK EXTCLKB ECLEXTCLK2 U48 DL1 U51 U45 CLKINB1 DL1OUT SACLKB CLKIN1 DL2OUT ENINTCLK SACLKLED CLKIN2 U42 FPGA2 U38 CLK MUX 1 NIMCLKOUT CT(5:0) U44 FPGA2 ECLCLKOUT1 INT_CLK 80Mhz Osc. ECLCLKOUT2 U39 DL2OUTB CLK0 TTCout(0-7) TTC(7-0)A CLK00 U44 TTC(7-0)B U44 CLKINB4 TIM Setup U47 DL4 SW7 Trigger Window WD(5:0) FPGA2 TIMCLK1L FPGA1 WS(5:0) DL4OUT FPGA2 TIMCLK2L SW10 FPGA2 U50 SW9 U69 DL TIMCLK3L Size U62 DL U63 DL U61 DL TRIGCLK DL4OUTB MRMW/MP v2.0 11-05-04 Delay Setup Size Comp. ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  13. Fail-over Clock MUX Fail-over Clock MUX 1 1 2 2 TIM-3 Clock Switching/TIM-OK TTCCLK TTCCLK-IN TIMCLK EXTCLK EXTCLK-IN SACLK INTCLK ENSACLK ENINTCLK Clock Detect Clock Detect Clock Detect FPGA2 6. Stat, 8 6. Stat, 9 0 0 EXTCLK-OK 1 ENEXTCLK TIM-OK ENTTCCLK 0.En, 8 12.RunEn, 0 TTCCLK-OK 1 RUNMODE 1.Cmd, 12 TTCREADY-IN QPLL_LOCKED MRMW/MP v2.0 18-06-04 ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

  14. RODBUSY(15) TIMOUTEN (enable for slot 13 only) RB_MASK(15) RBmask Backplane ROD Busy Output (NIM/TTL) PL167 RODBUSY(14) RODBUSY RB_MASK(14) Backplane (J3) ROD Busy Inputs RBmask RODBUSY(0) Front Panel ROD Busy Output (NIM/TTL) RB_MASK(0) V_RODBUSY LK4 RBmask Cmd, 8 ROD_CRATE_BUSYOUT LK1 Status, 7 1 RUNMODE SAMODE 1 Front Panel Busy Input (NIM) Cmd,12 Front Panel ROD Busy LED (‘RB’) 4 EXTRODBUSYIN EN_EXTRODBUSY 1 Run En, 8 LK7 Front Panel TIM Busy (ECL) EN_EXT_BUSY Front Panel Busy Input (ECL) NIMEXTBUSY Enables, 15 MEXTBUSYOUT PL41 EXT_BUSY ECLEXTBUSY Status, 1 Status, 0 1 EN_RODBUSY Run En, 7 Front Panel TIM Busy (NIM) RODBUSY LK6 Stand-Alone System BUSYOUT V_BUSY 1 Cmd, 7 Status, 3 Signal Deadtime Front Panel TIM Busy LED (‘TB’) EN_INT_BUSY Enables, 7 Test Busy INT_BUSY Status, 14 Status, 2 Burst Busy Status, 4 PLD/FPGA MRMW/MP v1.2 17-06-04 TIM Busy Signals Flow ATLAS SCT/Pixel TIM FDR/PRR Martin Postranecky: TIM HARDWARE

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