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Physics & Astronomy HEP Electronics

Physics & Astronomy HEP Electronics. TIM Firmware. ATLAS SCT TIM FDR/PRR 28 June 2004. Matthew Warren John Lane, Martin Postranecky. General. Firmware written in VHDL Maintainable. Support by almost all hardware. Used by other collaborators. Tools: Mentor Graphics FPGA Advantage 5.4

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Physics & Astronomy HEP Electronics

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  1. Physics & AstronomyHEP Electronics TIM Firmware ATLAS SCT TIM FDR/PRR 28 June 2004 Matthew WarrenJohn Lane, Martin Postranecky Firmware - Matt Warren

  2. General • Firmware written in VHDL • Maintainable. • Support by almost all hardware. • Used by other collaborators. • Tools: • Mentor Graphics FPGA Advantage 5.4 • Xilinx ISE 5.2i • Firmware structured in blocks similar to the old PLD sub-divisions. • Synchronous design principles followed. Firmware - Matt Warren

  3. FPGA/Code Structure • FPGA1 is the ‘Manager’ • VME Interface • Controls access to local bus • Manages resets • Can re-configure FPGA2’s PROM • Provides status information on FPGA2 etc. • FPGA2 is the ‘TIM Function’ • Front Panel Signals • J3 Backplane Signals • Sequencer RAM, ID FIFO’s are internal Firmware - Matt Warren

  4. TIM-3 Functional Layout Debug Header 8 Debug LEDs Debug Header 8 Debug LEDs 16 16 clk JTAG Config EEPROM FPGA1 FPGA1 VME Interface & Board Manager Clocks & Clk Control Config EEPROM FPGA2 FPGA2 TIM Function jtagx_en TTCrx fpga2_reset vme_select ROD Busy 16 vme_read Base Addr. Preset Switches vme_write 16 ROD Busy LEDs fpga2_ok FP and PO Resets Internal Trig, FER, ECR Board ID 8 8 Trigger Window 4 Debug Mode Select Switch 4 VME I/O Front-Panel Signals VME Control 16 spare_bus Back-Plane Signals 31 32 Addr(31:1) Address Bus 15 Front-Panel LEDs Data(31:0) Data Bus 32 MRMW v1.1 01-06-04 Firmware - Matt Warren

  5. TIM Hardware for Firmware • JTAG programmable PROMs used (Xilinx 18V) • FPGAs use Master Serial Mode for loading • Lower VME Address Bus (15:1) on both FPGAs • Allows local address decoding • Entire VME data-bus available to both FPGAs. • 32 bit registers if needed • Debug Hardware (see next slide) Firmware - Matt Warren

  6. Debug/Expansion Features • 16 line dedicated spare lines between FPGAs. • 16 line dedicated debug lines per FPGA • Connected to header – logic-analyser access • 8 debug lines/FPGA connected to SMD LEDs • Mode/Debug hex-switch connected to both FPGAs • minor changes in operation without downloading new code (e.g. LEDs map). • ROD Busy LEDs on front-panel available to code. • PCB version ID readable by FPGAs • Enough resources to add extra functions • e.g. Fixed Frequency Veto (more later) Firmware - Matt Warren

  7. FPGA Resource Utilisation • From Xilinx ISE Place & Route Report: • FPGA1 • Number of External GCLKIOBs 1 out of 4 25% • Number of External IOBs 161 out of 285 56% • Number of BLOCKRAMs 4 out of 14 28% • Number of SLICEs 280 out of 2352 11% • Number of DLLs 1 out of 4 25% • Number of GCLKs 1 out of 4 25% • Number of TBUFs 128 out of 2464 5% • FPGA2 • Number of External GCLKIOBs 2 out of 4 50% • Number of External IOBs 244 out of 325 75% • Number of BLOCKRAMs 64 out of 72 88% • Number of SLICEs 1843 out of 6912 26% • Number of DLLs 1 out of 4 25% • Number of GCLKs 1 out of 4 25% • Number of TBUFs 160 out of 7104 2% Firmware - Matt Warren

  8. Outstanding code • I2C interface to TTCrx • Works on TIM-2, so low priority • System for re-configuring FPGA2 from software • Firmware very ‘dumb’ – software will do the work. • Finalise Fixed Frequency Trigger Veto System • No big changes – just need iterate over best style of operation with community. Firmware - Matt Warren

  9. Simulation • Components Simulated using ModelSim • Most simulation fast enough to be carried out on the whole FPGA level • The VME interface was tested across both FPGAs including models of the external bus-transceivers. • Simulations are controlled via the bus interface. • Procedures have were written to do bus-like reads/writes. These allowed routines similar to those in the test software to be used. Firmware - Matt Warren

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