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Software of 80x86

Software of 80x86. Registers and Instructions Set. Registers. General Registers Segment Registers Status Rgisters. Control Registers Memory Management Registers FPU Registers Test Registers. 8086. Pentium. 8086 Registers. General Registers. 16 15. Stack Mechanism. PUSH AX =======

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Software of 80x86

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  1. Software of 80x86 Registers and Instructions Set

  2. Registers • General Registers • Segment Registers • Status Rgisters • Control Registers • Memory Management Registers • FPU Registers • Test Registers 8086 Pentium

  3. 8086 Registers

  4. General Registers

  5. 16 15

  6. Stack Mechanism PUSH AX ======= DEC SP [SP]=AH DEC SP [SP]=AL

  7. Events on Visual C++ • int p; ESP=0x0012F3B8 • p=test(3,4,0x1235) • push 5 ESP=0x0012F3B4 • [0x0012F3B4]=0x35 • push 4 ESP=0x0012F3B0 • push 3 ESP=0x0012F3AC • call test ESP=0x0012F3A8

  8. Inside the test int test(intx,inty,int z){ x2F0 55 push ebp x2F1 8B EC movebp,esp x2F3 81 EC CC 00 00 00 sub esp,0CCh x2F9 53 push ebx x2FA 56 push esi x2FB 57 push edi x2FC 8D BD 34 FF FFFF lea edi,[ebp-0CCh] x302 B9 33 00 00 00 mov ecx,33h x307 B8 CC CCCCCCmov eax,0CCCCCCCCh x30C F3 AB rep stosdwordptres:[edi] int u; u=x; x30E 8B 45 08 moveax,dwordptr [x] x311 89 45 F8 mov dword ptr [u],eax u=u+y; x314 8B 45 F8 moveax,dwordptr [u] x317 03 45 0C add eax,dwordptr [y] x31A 89 45 F8 movdwordptr [u],eax u=u+z; x31D 8B 45 F8 moveax,dwordptr [u] x320 03 45 10 add eax,dwordptr [z] x323 89 45 F8 mov dword ptr [u],eax return u; x326 8B 45 F8 moveax,dwordptr [u]

  9. EFLAG Register

  10. FPU Registers

  11. Memory Management Registers

  12. Control Registers

  13. Debug Registers

  14. Bit and Byte Order

  15. Data Types • Signed (integer) or unsigned (ordinal) • BCD : Packed (1 byte = 2 digits) or Unpacked • Floating point

  16. Memory Organization • Physical Memory Byte order – from 0 to 0FFFFFH (1 Megabytes) • Logical Address Segmentation translates this to a Linear Address SEGMENT:OFFSET

  17. Segmentation • Linear Address = Segment * 16 (or 0x10) + Offset • Example: Segment=0x2000 ; Offset = 0x444 • Linear Address = 0x2000*0x10+0x444=0x20444 • Segment Registers: CS, DS, SS, ES • Example CS=0x3000 ; DI=0x2345 • CS:DI=0x3000*0x10+0x2345=0x32345 • Mov AX , ES:DI ; AX = [ES*10H+DI] • Segment Size = 64K • Offset Size = from 0000 to FFFF)

  18. Real Mode Segmentation 16 bit Segment  X Y Z W T U V S 16 bit Offset  Linear 20/21 bit Address  1/0 L K N M S Always zero in 8086- A20M Pin determines the status in pentium If A20M = 0 then in real mode this bit is always Zero

  19. Default Segment Selection Rules

  20. Instructions Set Introduction to Instructions Set

  21. 8086 Instructions AAA AAD AAM AAS ADC ADD AND CALL CBW CLC CLD CLI CMC CMP CMPSB CMPSW CWD DAA DAS DEC DIV HLT IDIV IMUL IN INC INT INTO IRET JA JAE JB JBE JC JCXZ JE JG JGE JL JLE JMP JNA JNAE JNB JNBE JNC JNE JNG JNGE JNL JNLE JNO JNP JNS JNZ JO JP JPE JPO JS JZ LAHF LDS LEA LES LODSB LODSW LOOP LOOPE LOOPNE LOOPNZ LOOPZ MOV MOVSB MOVSW MUL NEG NOP NOT OR OUT POP POPA POPF PUSH PUSHA PUSHF RCL RCR REP REPE REPNE REPNZ REPZ RET RETF ROL ROR SAHF SAL SAR SBB SCASB SCASW SHL SHR STC STD STI STOSB STOSW SUB TEST XCHG XLATB XOR

  22. Instruction References • INTEGER INSTRUCTIONS • MMX™ TECHNOLOGY INSTRUCTIONS • FLOATING-POINT INSTRUCTIONS • SYSTEM INSTRUCTIONS

  23. System Instructions • LGDT Load global descriptor table (GDT) register • SGDT Store global descriptor table (GDT) register • LLDT Load local descriptor table (LDT) register • SLDT Store local descriptor table (LDT) register • LTR Load task register • STR Store task register • LIDT Load interrupt descriptor table (IDT) register • SIDT Store interrupt descriptor table (IDT) register • MOV Load and store control registers • LMSW Load machine status word : 286 Compatibility – 16 bits – Not to be used in pentium • SMSW Store machine status word • CLTS Clear the task-switched flag • ARPL Adjust requested privilege level • LAR Load access rights • LSL Load segment limit • VERR Verify segment for reading • VERW Verify segment for writing • MOV Load and store debug registers • INVD Invalidate cache, no writeback • WBINVD Invalidate cache, with writeback • INVLPG Invalidate TLB Entry • LOCK (prefix) Lock Bus • HLT Halt processor • RSM Return from system management mode (SSM) • RDMSR Read model-specific register • WRMSR Write model-specific register • RDPMC Read performance monitoring counters • RDTSC Read time stamp counter

  24. Segment Descriptor

  25. Application Descriptor Type

  26. System Descriptor Type

  27. Memory Management Registers

  28. RSM • Return From System Management Mode

  29. RDTSC • EDX:EAX ¬ TimeStampCounter • Opcode : 0F 31 • An internal Counter • A 64-bit MSR • Incremened by every clock cycle • Reset to 0 if CPU is reset • Time Stamp Counter is read if • CR4.TSD = 0 ; Time Stamp Disable • CR4.TSD = 1 && CPL = 0 (Protected Mode) • Exceptions • #GP(0) Protected Mode if TSD = 1 && CPL > 0 • #GP Real Mode if TSD = 1 • #GP(0) Virtual 8086 Mode if TSD = 1

  30. MSR • Model Specific Registers • 64 – bit • Undefined after CPU Reset • Unchanged on INIT • WRMSR is a Serializing Instruction • Purposes: testability, performance monitoring, and machine check errors • RDMSR - WRMSR • EDX:EAX  MSR (ECX) ; Model Specific Register (64-bit) • Opcode : 0F 32 / 0E 32 • MSR manipulation are privileged. • Not Valid in Virtual Mode • Always allowed in Real Mode • If ECX Wrong Exception #GP(0) / #GP occurs • CPUID: EDX.b5

  31. MSR : Registers

  32. Privileged Instructions • Instructions to be executed in Real Mode or Protection Mode with CPL = 0 • LIDT instruction - LGDT instruction - LMSW instruction - MOV for control and debug registers - CLTS instruction - HLT instruction - INVD instruction - WBINVD instruction - INVLPG instruction - RDMSR instruction • WRMSR instruction • RSM

  33. Serializing Instructions Serializing : Any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed. CPUID INVD INVLPG IRET IRETD LGDT LIDT LLDT LTR MOV to Debug Register MOV to Control Register RSM WBINVD WRMSR

  34. Floating-Point Instructions • DATA TRANSFER • BASIC ARITHMETIC • COMPARISON • TRANSCENDENTAL • LOAD CONSTANTS • FPU CONTROL

  35. FPU CONTROL • FINCSTP Increment FPU register stack pointer • FDECSTP Decrement FPU register stack pointer • FFREE Free floating-point register • FINIT Initialize FPU after checking error conditions • FNINIT Initialize FPU without checking error conditions • FCLEX Clear floating-point exception flags after checking for error • conditions • FNCLEX Clear floating-point exception flags without checking for error • conditions • FSTCW Store FPU control word after checking error conditions • FNSTCW Store FPU control word without checking error conditions • FLDCW Load FPU control word • FSTENV Store FPU environment after checking error conditions • FNSTENV Store FPU environment without checking error conditions • FLDENV Load FPU environment • FSAVE Save FPU state after checking error conditions • FNSAVE Save FPU state without checking error conditions • FRSTOR Restore FPU state • FSTSW Store FPU status word after checking error conditions • FNSTSW Store FPU status word without checking error conditions • WAIT/FWAIT Wait for FPU • FNOP FPU no operation

  36. LOAD CONSTANTS • FLD1 Load +1.0 • FLDZ Load +0.0 • FLDPI Load p • FLDL2E Load log2e • FLDLN2 Load loge2 • FLDL2T Load log210 • FLDLG2 Load log102

  37. TRANSCENDENTAL • FSIN Sine • FCOS Cosine • FSINCOS Sine and cosine • FPTAN Partial tangent st(0)=tan(st(0)); 1push register stack • FPATAN Partial arctangent • F2XM1 st(0)=2^st(0) - 1 • FYL2X y*log2x • FYL2XP1 y*log2(x+1)

  38. COMPARISON • FCOM m32/m64/st(I)/none st(0):src flags:c0,c1,c2 • FCOMP Compare real and pop • FCOMPP Compare real and pop twice • FUCOM Unordered compare real Does not generate an invalid-arithmetic-operand exception • FUCOMP Unordered compare real and pop • FUCOMPP Unordered compare real and pop twice • FICOM m16/m32 Compare with integer • FICOMP Compare integer and pop • FCOMI Compare real and set EFLAGS(Z,P,C) • FUCOMI Unordered compare real and set EFLAGS • FCOMIP Compare real, set EFLAGS, and pop • FUCOMIP Unordered compare real, set EFLAGS, and pop • FTST Test real Compare St(0):0.0 • FXAM Examine real

  39. FXAM C1 ¬ sign bit of ST; (* 0 for positive, 1 for negative *)

  40. BASIC ARITHMETIC Floatng point Addition/subtraction FSUBR, FSUBRP, FISUBR Reverse Subtraction FMUL Multiply real FMULP Multiply real and pop FIMUL Multiply integer FDIV Divide real FDIVP Divide real and pop FIDIV Divide integer FDIVR, FDIVRP, FIDIVR Reverse Division FPREM Partial remainder FPREMI IEEE Partial remainder st(0)%=st(1) FABS Absolute value FCHS Change sign FRNDINT Round to integer FSCALE Scale by power of two st(0)=st(0)*2^st(1) FSQRT Square root FXTRACT st(0)=exponent(st(0)) significandregister stack

  41. Floating Point Addition/Subtraction

  42. DATA TRANSFER FLD m32real/m64real/m80real/st(I) push onto FPU register stack FST m32real/m64real/st(I) store st(0) on m32…. FSTP m32real/m64real/m80real/st(I) FST & pop stack FILD m16/m32/m64 Load integer. push onto FPU register stack FIST Store integer FISTP Store integer and pop FBLD Load BCD FBSTP Store BCD and pop FXCH st(I)/none Exchange registers st(0) and st(I)/st(1) FCMOVE Floating-point conditional move if equal FCMOVNE Floating-point conditional move if not equal FCMOVB Floating-point conditional move if below FCMOVBE Floating-point conditional move if below or equal FCMOVNB Floating-point conditional move if not below FCMOVNBE Floating-point conditional move if not below or equal FCMOVU Floating-point conditional move if unordered FCMOVNU Floating-point

  43. INTEGER INSTRUCTIONS • DATA TRANSFER INSTRUCTIONS • BINARY ARITHMETIC INSTRUCTIONS • DECIMAL ARITHMETIC INSTRUCTIONS • LOGIC INSTRUCTIONS • SHIFT AND ROTATE INSTRUCTIONS • BIT AND BYTE INSTRUCTIONS • CONTROL TRANSFER INSTRUCTIONS • STRING INSTRUCTIONS • FLAG CONTROL INSTRUCTIONS • SEGMENT REGISTER INSTRUCTIONS • MISCELLANEOUS INSTRUCTIONS

  44. MISCELLANEOUS INSTRUCTIONS • LEA Load effective address • NOP No operation • UB2 Undefined instruction • XLAT/XLATB Table lookup translation • D7 XLAT m8 AL = DS:[(E)BX + unsigned AL] • D7 XLATB • CPUID Processor Identification

  45. CPUID Input: EAX Output: EAX, EBX, ECX, and EDX

  46. Encoding of Cache and TLB Descriptors

  47. CPUID : EAX =1 • First One: • Model—0001B • • Family—0110B • • Processor Type—00B

  48. Feature Flags Returned in EDX Register

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