Chapter 5
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Chapter 5. Instructor: Mozafar Bag-Mohammadi Spring 2010 Ilam University. Our Methodology. Only flip-flops All on the same edge (e.g. falling) All with same clock No need to draw clock signals All logic finishes in one cycle. Our Methodology, cont’d. No clock gating!

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Chapter 5

Chapter 5

Instructor:

Mozafar Bag-Mohammadi

Spring 2010

Ilam University


Our methodology

Our Methodology

  • Only flip-flops

  • All on the same edge (e.g. falling)

  • All with same clock

    • No need to draw clock signals

  • All logic finishes in one cycle


Our methodology cont d

Our Methodology, cont’d

  • No clock gating!

    • Book has bad examples

  • Correct design:


Datapath 1 cpi

Datapath – 1 CPI

  • Assumption: get whole instruction done in one long cycle

  • Instructions:

    • add, sub, and, or slt, lw, sw, & beq

  • To do

    • For each instruction type

    • Putting it all together


Fetch instructions

Fetch Instructions

  • Fetch instruction, then increment PC

    • Same for all types

  • Assumes

    • PC updated every cycle

    • No branches or jumps

  • After this instruction fetch next one


Alu instructions

ALU Instructions

  • and $1, $2, $3 # $1 <= $2 & $3

  • E.g. MIPS R-format

    Opcodersrtrdshamtfunction

    655556


Load store instructions

Load/Store Instructions

  • lw $1, immed($2) # $1 <= M[SE(immed)+$2]

  • E.g. MIPS I-format:

    Opcodertrtimmed

    65516


Branch instructions

Branch Instructions

  • beq $1, $2, addr # if ($1==$2) PC = PC + addr<<2

  • Actually

    newPC = PC + 4

    target = newPC + addr << 2 # in MIPS offset from newPC

    if (($1 - $2) == 0)

    PC = target

    else

    PC = newPC


Branch instructions1

Branch Instructions


All together

All Together


Control overview

Control Overview

  • Single-cycle implementation

    • Datapath: combinational logic, I-mem, regs, D-mem, PC

      • Last three written at end of cycle

    • Need control – just combinational logic!

    • Inputs:

      • Instruction (I-mem out)

      • Zero (for beq)

    • Outputs:

      • Control lines for muxes

      • ALUop

      • Write-enables


Control overview1

Control Overview

  • Fast control

    • Divide up work on “need to know” basis

    • Logic with fewer inputs is faster

  • E.g.

    • Global control need not know which ALUop


Alu control

ALU Control

  • Assume ALU uses


Alu control1

ALU Control

  • ALU-ctrl = f(opcode,function)

  • To simplify ALU-ctrl

    • ALUop = f(opcode)

      2 bits6 bits


Alu control2

ALU Control

  • ALU-ctrl = f(ALUop, function)

  • 3 bits2 bits6 bits

  • Requires only five gates plus inverters


Control signals needed 5 19

Control Signals Needed (5.19)


Global control

Global Control

  • R-format: opcodersrtrdshamtfunction

    655556

  • I-format: opcodersrtaddress/immediate

    65516

  • J-format: opcodeaddress

    626


Global control1

Global Control

  • Route instruction[25:21] as read reg1 spec

  • Route instruction[20:16] are read reg2 spec

  • Route instruction[20:16] (load) and instruction[15:11] (others) to

    • Write reg mux

  • Call instruction[31:26] op[5:0]


Global control2

Global Control

  • Global control outputs

    • ALU-ctrl- see above

    • ALU src- R-format, beq vs. ld/st

    • MemRead- lw

    • MemWrite- sw

    • MemtoReg- lw

    • RegDst- lw dst in bits 20:16, not 15:11

    • RegWrite- all but beq and sw

    • PCSrc- beq taken


Global control3

Global Control

  • Global control outputs

    • Replace PCsrc with

      • Branch beq

      • PCSrc = Branch * Zero

  • What are the inputs needed to determine above global control signals?

    • Just Op[5:0]


Global control fig 5 20

Global Control (Fig. 5.20)

  • RegDst = ~Op[0]

  • ALUSrc = Op[0]

  • RegWrite = ~Op[3] * ~Op[2]


Global control4

Global Control

  • More complex with entire MIPS ISA

    • Need more systematic structure

    • Want to share gates between control signals

  • Common solution: PLA

    • MIPS opcode space designed to minimize PLA inputs, minterms, and outputs

  • See MIPS Opcode map (Fig A.19)


Control signals add jumps

Control Signals; Add Jumps


Control signals w jumps 5 29

Control Signals w/Jumps (5.29)


What s wrong with single cycle

Instructions

Cycles

Time

X

X

Instruction

Program

Cycle

(code size)

(CPI)

(cycle time)

What’s wrong with single cycle?

  • Critical path probably lw:

    • I-mem, reg-read, alu, d-mem, reg-write

  • Other instructions faster

    • E.g. rrr: skip d-mem

  • Instruction variation much worse for full ISA and real implementation:

    • FP divide

    • Cache misses (what the heck is this? – chapter 7)


Single cycle implementation

Single Cycle Implementation

  • Solution

    • Variable clock?

      • Too hard to control, design

    • Fixed short clock

      • Variable cycles per instruction


Multi cycle implementation

Multi-cycle Implementation

  • Clock cycle = max(i-mem,reg-read+reg-write, ALU, d-mem)

  • Reuse combination logic on different cycles

    • One memory

    • One ALU without other adders

  • But

    • Control is more complex

    • Need new registers to save values (e.g. IR)

      • Used again on later cycles

      • Logic that computes signals is reused


High level multi cycle data path

High-level Multi-cycle Data-path

  • Note:

    • Instruction register, memory data register

    • One memory with address bus

    • One ALU with ALUOut register


Comment on busses

Comment on busses

  • Share wires to reduce #signals

    • Distributed multiplexor

  • Multiple sources driving one bus

    • Ensure only one is active!


Multi cycle ctrl signals fig 5 32

Multi-cycle Ctrl Signals (Fig 5.32)


Multi cycle datapath

Multi-cycle Datapath


Multi cycle steps

Multi-cycle Steps


Multi cycle control

Next

State

Current

Next

state

State Fn

outputs

Inputs

Output

Fn

Multi-cycle Control

  • Function of Op[5:0] and current step

  • Defined as Finite State Machine (FSM) or

    • Micro-program or microcode (later)

  • FSM – App. B

    • State is combination of step and which path


Finite state machine fsm

Finite State Machine (FSM)

  • For each state, define:

    • Control signals for datapath for this cycle

    • Control signals to determine next state

  • All instructions start in same IF state

  • Instructions terminate by making IF next

    • After proper PC update


Multi cycle example and

IF

ID

MemRead

ALUSrcA=0

IorD = 0

IRWrite

ALUSrcB = 01

ALUOp = 00

PCWrite

PCSrc = 00

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

Start

LW | SW

J

RRR

BEQ

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCond

PCSource = 01

PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

EX

LW

SW

MemRead

IorD = 1

MemWrite

IorD = 1

RegDst = 1

RegWrite

MemtoReg = 0

WB

MEM

RegDst = 0

RegWrite

MemtoReg = 1

WB

Multi-cycle Example (and)


Multi cycle example and1

Multi-cycle Example (and)


Nuts and bolts more on fsms

Nuts and Bolts--More on FSMs

  • You will be using FSM control for your processor implementation

  • You will be producing the state machine and control outputs from binary (ISA/datapath controls)

  • There are multiple methods for specifying a state machine

    • Moore machine (output is function of state only)

    • Mealy machine (output is function of state/input)

  • There are different methods of assigning states


Fsms state assignment

FSMs--State Assignment

  • State assignment is converting logical states to binary representation

  • Is state assignment interesting/important?

    • Judicious choice of state representation can make next state fcn/output fcn have fewer gates

    • Optimal solution is hard, but having intuition is helpful (CAD tools can also help in practice)


State assignment example

State Assignment--Example

  • 10 states in multicycle control FSM

    • Each state can have 1 of 16 (2^4) encodings with “dense” state representation

    • Any choice of encoding is fine functionally as long as all states are unique

  • Appendix C-26 example: RegWrite signal


State assignment regwrite signal

IF

ID

MemRead

ALUSrcA=0

IorD = 0

IRWrite

ALUSrcB = 01

ALUOp = 00

PCWrite

PCSrc = 00

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

Start

LW | SW

J

RRR

BEQ

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCond

PCSource = 01

PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

EX

LW

SW

MemRead

IorD = 1

MemWrite

IorD = 1

RegDst = 1

RegWrite

MemtoReg = 0

WB

MEM

RegDst = 0

RegWrite

MemtoReg = 1

WB

State Assignment,RegWrite Signal

State 0

State 1

State 2

State 6

State 8

State 9

State 4

State 7

State 5

State 3

State 7 (0111b)

State 9 (1001b)

State 4 (0100b)

State 8 (1000b)

Original: 2 inverters, 2 and3s, 1 or2

New: No gates--just bit 3!


Multi cycle example lw

IF

ID

MemRead

ALUSrcA=0

IorD = 0

IRWrite

ALUSrcB = 01

ALUOp = 00

PCWrite

PCSrc = 00

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

Start

LW | SW

J

RRR

BEQ

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCond

PCSource = 01

PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

EX

LW

SW

MemRead

IorD = 1

MemWrite

IorD = 1

RegDst = 1

RegWrite

MemtoReg = 0

WB

MEM

RegDst = 0

RegWrite

MemtoReg = 1

WB

Multi-cycle Example (lw)


Multi cycle example lw1

Multi-cycle Example (lw)


Multi cycle example sw

IF

ID

MemRead

ALUSrcA=0

IorD = 0

IRWrite

ALUSrcB = 01

ALUOp = 00

PCWrite

PCSrc = 00

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

Start

LW | SW

J

RRR

BEQ

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCond

PCSource = 01

PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

EX

LW

SW

MemRead

IorD = 1

MemWrite

IorD = 1

RegDst = 1

RegWrite

MemtoReg = 0

WB

MEM

RegDst = 0

RegWrite

MemtoReg = 1

WB

Multi-cycle Example (sw)


Multi cycle example sw1

Multi-cycle Example (sw)


Multi cycle example beq t

IF

ID

MemRead

ALUSrcA=0

IorD = 0

IRWrite

ALUSrcB = 01

ALUOp = 00

PCWrite

PCSrc = 00

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

Start

LW | SW

J

RRR

BEQ

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCond

PCSource = 01

PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

EX

LW

SW

MemRead

IorD = 1

MemWrite

IorD = 1

RegDst = 1

RegWrite

MemtoReg = 0

WB

MEM

RegDst = 0

RegWrite

MemtoReg = 1

WB

Multi-cycle Example (beq T)


Multi cycle example beq t1

Multi-cycle Example (beq T)


Multi cycle example beq nt

Multi-cycle Example (beq NT)


Multi cycle example j

IF

ID

MemRead

ALUSrcA=0

IorD = 0

IRWrite

ALUSrcB = 01

ALUOp = 00

PCWrite

PCSrc = 00

ALUSrcA = 0

ALUSrcB = 11

ALUOp = 00

Start

LW | SW

J

RRR

BEQ

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 10

ALUSrcA = 1

ALUSrcB = 00

ALUOp = 01

PCWriteCond

PCSource = 01

PCWrite

PCSource = 10

ALUSrcA = 1

ALUSrcB = 10

ALUOp = 00

EX

LW

SW

MemRead

IorD = 1

MemWrite

IorD = 1

RegDst = 1

RegWrite

MemtoReg = 0

WB

MEM

RegDst = 0

RegWrite

MemtoReg = 1

WB

Multi-cycle Example (j)


Multi cycle example j1

Multi-cycle Example (j)


Summary

Summary

  • Processor implementation

    • Datapath

    • Control

  • Single cycle implementation

  • Next: microprogramming


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