Interconnect Verification for SOC

1. Interconnect Verification for SOC Jing-Yang Jou Department of Electronics Engineering National Chiao Tung University Hsinchu, Taiwan E-mail: jyjou@ee.nctu.edu.tw URL: http://eda.ee.nctu.edu.tw/jyjou

2. Outlines • Interconnect verification • Motivation • The port order fault (POF) model • The integration verification • Automatic verification pattern generation (AVPG)

3. Verification Throughput • The factors that govern simulation-based verification throughput: • The speed of the simulator • The complexity of the design • The size of the test (verification) bench

4. System Design Verification • SOB verification • Components are designed, verified, manufactured, and tested (fault free building blocks ) • Limit to detecting faults in the interconnection among the components • SOC verification • Components are design error free building blocks • Limit to detecting the misplacements of the interconnection among the components • Reduce the verification complexity • Port Order Fault (POF) model

5. Outlines • Interconnect verification • Motivation • The port order fault (POF) model • The integration verification • Automatic verification pattern generation (AVPG)

6. Basic Assumptions of the POF Model • A faulty component has at least two I/O ports misplaced in the integrated design • Components (IPs) are fault free • Only the interconnection among the components could be faulty

7. Type-I POF POF Variety (1/3) A3 A2 A1 A0 B3 B2 B1 S0 4-bit Adder COUT CIN S3 S2 S1 B0

8. POF Variety (2/3) • Type-II POF A0 A1 A2 A3 B3 B2 B1 B0 4-bit Adder COUT CIN S3 S2 S1 S0

9. POF Variety (3/3) • Type-III POF A3 A2 A1 A0 B3 B2 B1 B0 4-bit Adder COUT CIN S0 S1 S2 S3

10. Typical Errors in the Integrated SOC Design • VCs are connected with wrong port orders • VCs with incompatible communication protocols are directly connected • PCI vs. AMBA • Interface parameters are not properly configured • Baud rate 2400 vs. baud rate 9600 TX TX TX TX RX RX RX RX

11. Outlines • Interconnect verification • Motivation • The port order fault (POF) model • The integration verification • Automatic verification pattern generation (AVPG)

12. Apply patterns Observe responses Interconnect Testing IP1 IP2 wrapper wrapper

13. Apply patterns Observe responses Interconnect Verification IP1 IP2 wrapper wrapper

14. Observe Apply patterns responses R T to PIs from POs Interconnect A Interconnect C BLK1 BLK6 BLK4 Output Verification BLK2 Patterns Analyzer Generation BLK5 BLK3 Interconnect B Integration Verification

15. Integration Verification • Verifying the interconnect A, B, and C • Apply patterns T to PIs and observe responses R from POs • The generation of T depends on the functionalities of BLK1 ~BLK6 • Complexity of cores increases and more cores are involved • T becomes harder to generate • Solution ?

16. System Chip with P1500 Cores

17. Integration Verification • IEEE P1500 • Establishes the mechanism that test patterns of any CUT can be applied to PIs of the system chip and test results can be propagated to POs of the system chip via user defined TAMs • Pre-defined operations: core-internal test, core-external test, bypass, isolation, and normal modes

18. Apply patterns Observe responses Interconnect Verification IP1 IP2 wrapper wrapper

19. Apply patterns Observe T to PIs responses R from POs external test mode BLK1 wrapper Interconnect A core BLK4 normal mode 1 wrapper external test mode BLK2 core Verification wrapper Output 4 Patterns core Analyzer 2 Generation BLK3 Integration Verification

20. Apply patterns Observe T to PIs responses R from POs BLK1 bypass mode wrapper Interconnect C core external test mode normal mode BLK6 BLK4 1 Si So wrapper wrapper BLK2 bypass mode core core Verification Output wrapper 4 6 Patterns Analyzer core Generation 2 Si So BLK5 BLK3 Verified Interconnect B Integration Verification

21. Verification Features • Reduce the complexity of POF verification • Focus on the functionality of the added block solely when generating the verification patterns • Exercise the core via the normal operation path to verify the interconnect • Consistency check of simulation results and expected ones • Reuse the hardware overhead incurred in the testing phase

22. Outlines • Interconnect verification • Motivation • The port order fault (POF) model • The integration verification • Automatic verification pattern generation (AVPG)

23. Automatic Verification Pattern Generation (AVPG) • Fault Activation • All N!-1 POFs have to be activated • Fault Propagation • Determined by simulation outputs • Undetected Port Sequences (UPSs) Calculation • Outputs analysis

24. Experimental Results

25. Conclusions • Interconnect verification provides a sufficient high level of confidence on verifying the correctness of the core-based system (SOC) design • Proposed AVPG can generate efficient verification patterns with high POF coverage