soc interconnect modeling venkata krishna n dhulipala 11 20 2008
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SoC Interconnect Modeling Venkata Krishna N. Dhulipala 11/20/2008. Relevance and Motivation. Most embedded systems today are built using SoC (System on Chip) technology As technology advances delay of transistors and local interconnects scales down augmenting clock rates

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relevance and motivation
Relevance and Motivation
  • Most embedded systems today are built using SoC (System on Chip) technology
  • As technology advances delay of transistors and local interconnects scales down augmenting clock rates
  • Since chip area is projected to increase, length of global interconnects increases and therefore their delay
interconnect modeling

w s

l

t

h

Interconnect Modeling
  • Resistance: R = (ρ/t ). (l/w), ρ=resistivity is constant for given metal
interconnect modeling1
Interconnect Modeling
  • Capacitance:

C = (εox/h) . wl

  • Coupling capacitance with adjacent wires ignored here – Gives rise to crosstalk
  • Putting resistance and capacitance together  Delay, Τpd = RC
  • A more detailed capacitance model is discussed in the report
interconnect modeling2
Interconnect Modeling
  • Inductance: Significant at higher frequencies, since impedance Z=R+jwL
  • Introduces second order effects like,
    • (a) Over/under-shoot edges,
    • (b) L di/dt voltage drop,
    • (c) Long range crosstalk, and
    • (d) f-dependent R
improve timing
Improve Timing
  • Add signal Repeaters
  • Effectively partition On and Off-chip interconnects
  • Space and ground shielding to eliminate crosstalk
  • Report shows mathematical derivations to minimize delay by addition of repeaters and partitioning
current and future work
Current and Future Work
  • Current Tools – Mantle by Magma (place and route), Primtime/Primetime-SI by Synopsys (timing and signal integrity analysis), Allegro by Cadence (chip-to-board interconnect modeling)
  • Future & Research
    • Parallel Repeater-Insertion – To account for inductance effects
    • Interconnect delay aware RTL bus architectures
    • Noise-rejection interconnect design
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