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Interconnect Verification 1

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Interconnect Verification 1

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What is Interconnect Verification?

Why Interconnect Verification?

Interconnect Verification Algorithms

Goal

Understand IV problem

Understand IV algorithms

Interconnect Verification 1Are two netlists equivalent?

If not, where are they different?

useless without this

Sometimes called layout vs. schematic (LVS)

Goals

determine if layout implements schematic

map layout to schematic for back-annotation

Approach

graph isomorphism

4/2

4/2

What is Interconnect Verification?Equality,

Differences

Circuit

Extractor

Interconnect

Verification

Extracted

Netlist

Schematic --> layout an imperfect process

bugs in layout synthesis tools

hand design

Schematic --> layout transformations

swap gate inputs

AND-OR => NAND-NAND structures

Back-annotation

user may not label all nets

map geometry at (x,y) to net in schematic

e.g. insert extracted parasitic into schematic

A

B

vs.

B

A

4/2

4/2

Why Interconnect Verification?vs.

device nodes

type, terminal labels

attributes, e.g. size

net nodes

bipartite graph

edges only between device and net nodes

Perform graph isomorphism test

given graphs G1 and G2

is there a 1:1 function f

mapping vertices of G1 onto vertices of G2

such that x and y are adjacent in G1 (connected by an edge) iff f(x) and f(y) are adjacent in G2

x

x

g

g

D

D

x

x

x

x

E

E

g

g

x

x

Interconnect Verification Algorithmscompute vertex invariants or color

function of vertex properties - labels, degree, etc.

function of neighboring vertices - type, color, equivalence class

partition vertices by color into equivalence classes

recolor based on new neighboring classes

repeat until single vertex in each class or no progress

sort each graph by vertex color and compare lists

Time Complexity

unknown in general case (NP-Intermediate)

known algorithms are exponential in worst case

partitioning is O(V) in practice

if graphs are equivalent and unambiguous

Graph Isomorphismdo {

for i = 0...V do {

G.vertex[i].color = VertexColor(G.vertex[i])

AddToClass(G.vertex[i].color, G.vertex[i])

}

} until all vertex[i].color are unique or no progress

SortByColor(G)

}

for i = 0...V do {

if G1.vertex[i].color != G2.vertex[i].color

report error

}

Partitioning Algorithm{

append(class[color],vertex)

vertex.class = class[color]

}

VertexColor(vertex)

{

compute color from vertex properties

current vertex color,

neighboring vertex colors

}

Partitioning AlgorithmExample

a

a

b

c

a

b

a

a: 3 edges

b: 4 edges

c: 2 edges

a3

a1

b1

a3a

a1

b1

c

c

c

a3

b2

a2

a1: a,b,c

a2: a,b,b

a3: a,a,b

b1: a,a,b,c

b2: a,a,a,b

a3b

b2

a2

a3a: a1,a3,b2

a3b: a3,a2,b2

x

x

x

g

g

g

g

D

D

D

D

x

x

x

x

x

x

x

x

E

E

E

E

g

g

g

g

x

x

x

x

x

x

g

g

D

D

x

x

x

x

E

E

g

g

x

x

GEMINI ExampleN2

DD

DD

N4

N2

N2

DE

DE

N2

(N2 (x: DD DD))

(DD (g: N4) (x: N2 N4))

(DD (g: N2) (x: N2 N2))

(N2 (x: DD DE))

(N2 (g: DD DE))

(DE (g: N4 (x: N2 N2))

(DE (g: N2) (x: N2 N4))

(N2 (x: DE DE))

x

g

g

P

P

x

x

x

x

g

g

P

P

x

x

x

x

x

x

N

N

N

N

g

g

g

g

x

x

x

x

CMOS ExampleNxP

DP

N2xP

DP

NgPgN

NxP2xN

NgPgN

DN

DN

NxP

N2xN

color devices by type

color nets by adjacent device, terminal type

create graph

x

g

g

P

P

x

x

x

x

g

g

P

P

x

x

x

x

x

x

N

N

N

N

g

g

g

g

x

x

x

x

CMOS ExampleNxP

NxP

DPgPgNxP2xP

DPgPgNxP2xP (P1)

N2xP

N2xP

DPgPgN2xPxP2xN

DPgPgN2xPxP2xN (P2)

NgPgN

NgP1gN

NxP2xN

NgPgN

NxP2xN

NgP2gN

DNgP1gN2xNxP2xN

DNgPgN2xNxP2xN

DNgP2gN2xNxP2xN

N2xN

N2xN

DNgPgN2xNxP2xN

color nets by adjacent devices

color devices by adjacent nets

all vertices uniquely colored

color devices by adjacent nets

colori+1 = f(colori, g(colorneighbor1, edge-classneighbor1), g(colorneighbor2, edge-classneighbor2),...)

edge class - e.g. source, drain, gate

g - source and drain are equivalent

hash to get compact colors - color is an integer

Signatures

snext = scurrent + csdssource + csdsdrain + cgsgate

s - signature

c - weights to treat transistor terminals differently

snetnext = snetcurrent + wisdevice i + wjsdevice j + ...

w - weights for terminal types

Coloring Functionsrecoloring is main computation

want to be fast

ideally look only at attributes of vertex, adjacent vertices

can initially look at very few attributes

only look at more if recoloring stops

Good Hash Function

hash/signature collisions slow down convergence

mistakenly give two vertices the same color

later have to detect they are really different

iterations must continue until all vertices are uniquely colored

Compromise between the two

Coloring Function IssuesRecolor only on frontier

only color vertices adjacent to singleton classes

likely to provide most useful coloring

singleton classes will not be recolored

only color vertices adjacent to recolored vertices

only these vertices can change color

Speed

2-10X speedup

recolor each vertex ~2 times

speed limited by netlist I/O

B

B

B

B

B

B

B

B

A

A

B

C

RefinementsMatching non-unique G1 and G2 classes cannot be subdivided

causes

invariant not sufficiently powerful - unlikely in real circuits

circuit is automorphism - ring oscillator, logic equivalence

force vertex in G1 and G2 to be equivalent and continue

may have to backtrack

require user to add labels

Ambiguous CircuitsA

B

vs.

B

A

Legal mappings:

{A,a} (B,b} {C,c}

{A,b} {B,c} {C,a}

{A,c} {B,a} {C,b}

vs.

A

B

C

a

b

c

Vdd connection missing from pullup transistor

result - Vdd vertices are colored differently in G1 and G2

different degree => different color

color difference rapidly propagated to all vertices

no vertex colors match, no useful diagnostic

Solution

label classes that do not have corresponding class in other graph as suspect

corresponding = same vertex count, same color

remove suspect vertices from class refinement process

do not use when recoloring other vertices

when no further recoloring possible, examine suspects

differences will be isolated to suspect classes

e.g. difference in Vdd net, pullup transistor

Finding Circuit Errors