Final Year Project “A Remote FPGA Laboratory Environment” Progress Presentation By David Hehir

1. Final Year Project “A Remote FPGA Laboratory Environment” Progress Presentation By David Hehir Supervisor: Dr. Fearghal Morgan

2. Presentation Overview • Project Background • System Overview • Goals and Requirements • Current Work/Ideas • Status Summary • Future Work • References

3. Project Background The goal of the project is to create a “Remote FPGA Laboratory” in which a user can: • Connect to the remote server PC • Upload/compile/run code on FPGA from the server PC • Get live webcam feedback of the board running the code • Have access to other functionality such as manipulation of buttons and switches on the board via a GUI

4. System Overview

5. Project Goals and Requirements • Create project webpage including all documents, status and categorised links, application downloads as each revision has been completed. • Develop top level drawings and specifications illustrating all elements of the project to date. • Develop GUI to incorporate remote/local hardware selection option and radio buttons on GUI to enable 8 x virtual toggle switches and 4 x virtual spring-loaded switches. These switch settings will be transferred to FPGA. • Incorporate security on remote computer/server running board. • Include settings to manage filespace and possibly chat to other users. • Future work will include possible implementation on NEXYS Spartan-3 system, its GUI and USB interface.

6. Applied VHDL Course & code • Part of our course in VHDL this year was to complete an Image Processing System implementing VHDL capture, testbench, simulation, synthesis, FPGA implementation and hardware test.

7. UART is responsible for encoding/decoding data • The IOCtrlr state machine reads and decodes commands received by the UART and controls the operation of Control and Status Register Blocks (CSR). • Depending on the command sent to the board CSR read/write can be performed. The display controller drives multiplexed 7 segment displays which are used to display commands sent and received by the board. • The values stored in the CSR Registers are used to control other parts of the system developed in latter parts of the course.

8. Block Layout of Updated System • Skeleton will mostly remain the same • Inputs: ext_sw, ext_btn, ext_rst and int_sw, int_btn and int_rst • The user will be able to control these switches/buttons • Not be allowed to control the reset as this could destroy the system’s operation.

9. Graphical User Interface

10. Synthesizing User Code • Because of the potential of a user uploading erroneous/malicious code to the system, which could cause damage, the user will not be allowed to upload a bitstream file directly to the server. There are two options available to us: • The user would download a version of the template/skeleton and fill it with their code, compile and check it for errors locally and then upload to the system. • The user could submit their code to the system by uploading it to their filespace. But it would have to be uploaded in a Zip file format and the system would create a new project for each user, then the skeleton/template files would be in this folder together with the user’s VHDL code.

11. Remote Access Requirements and Security Issues • VNC Client – www.realvnc.com - downloadable freeware client for connecting to remote machines, Once the user logs on, restricted remote access will be given to them, primarily running Xilinx/ISE Tools and allowing them live view of the webcam. • Security Issues - connection will be password protected and may be restricted to certain IP addresses. Users from a certain area or domain may only be granted access, such as student complexes/villages in and around Galway. More to follow on this later. Logon accounts perhaps to be created at discretion of technicians/Fearghal.

12. Future Work And Work In Progress • Include settings to manage filespace and possibly chat to other users(Java). • Completing the VB GUI and extra functionality. • Implementation on NEXYS Spartan-3 system, its GUI and USB interface.

13. Personal Goals • To strive to complete the project in its entirity and avail of any free time by spending it in the Labs. • To cover all possible issues so as to avoid serious problems down the line. • To keep my supervisor updated, and have regular progress meetings, update the project website and maintain it.

14. Status Summary • The final project has to be submitted by March 21st. • Completed nearly all VHDL code for the prototype design. • Beginning VB coding for GUI. • I am slightly behind at the moment due to loss of work by laptop breaking down over Christmas but am catching up. • The end goal is to have created a fully functional Virtual FPGA Laboratory for students to use over the internet.

15. Resources • Would like to thank the technicians, Myles and Martin who have so far been very helpful in setting up certain applications for me. • Fearghalfor being very obliging with his time and meetings when I have issues. • Other helpful resources have been the EE427 project code and notes in the last semester due to it’s relevance to my project. • Internet – various manuals, sites for coding VB and C++

16. Thank you! • Any Questions?