Design and Implementation of VLSI Systems (EN1600) Lecture 20: Combinational Circuit Design (2/3)

1. Design and Implementation of VLSI Systems (EN1600) Lecture 20: Combinational Circuit Design (2/3) Prof. Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. Let’s get rid of pMOS • Reduced the capacitance and improved the delay • Increased static power consumption Implementing a large resistive load in CMOS is not readily available [see subsection 2.5.4]

3. 2. Pseudo-nMOS circuits • Use a pull-up transistor that is always ON • Issues: • Ratio or relative strength • Make pMOS about ¼ effective strength of pulldown network [see subsection 2.5.4]

4. Design for unit current on output to compare with unit inverter. pMOS fights nMOS psuedo-nMOS is slower on the average than CMOS but it works well for wide NOR gates Logical effort of pseudo-nMOS gates logical effort independent of number of inputs!

5. Pseudo-nMOS draws power whenever Y = 0 Called static power P = I•VDD A few mA / gate * 1M gates would be a problem This is why nMOS went extinct! Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use Pseudo-nMOS power

6. Ganged CMOS Traditional pseudo-nMOS • When A=B=0: • both pMOS turn on in parallel pulling the output high fast • When both inputs are ‘1’: • both pMOS transistors turn off saving power over psuedo-nMOS • When one is ‘1’ or one is ‘0’ then it is just like the pseudo-nMOS case

7. Seeks the performance of pseudo-nMOS without the static power consumption 3. Cascode Voltage Switch Logic (CVSL) • CVSL disadvantages: • Require input complement • NAND gate structures can be tall and slow

8. 4. Pass Transistor Logic • Advantage: • just uses two transistors • Problem: • ‘1’ is not passed perfectly • cannot the output to the input of another gate

9. A Pass-Transistor A F Network B B (a) A Inverse A F Pass-Transistor B Network B B B B B B B A A A B F=AB A B F=A ÅB F=A+B (b) A A A B F = AB A F = A ÅB F = A+B B EXOR/NEXOR AND/NAND OR/NOR Complementary Pass Transistor Logic (CPTL) • Complementary data inputs and outputs are available • Very suitable for XOR realization (compare to traditional CMOS) • Interconnect overhead to route the signal and its complement

10. 3.0 In Out V 2.0 [V] DD x e V g DD Level Restorer a t l o M V r 1.0 B M 2 X M A 0.0 Out n 0 0.5 1 1.5 2 Time [ns] M 1 A better design: full swing; reduces static power Possible solution: interface to a CMOS inverter Threshold voltage loss causes static power consumption (AKA Lean Integration with Pass Transistors - LEAP)

11. In pass-transistor circuits, inputs are also applied to the source/drain terminals. Circuits are built using transmission gates. Pass Transistor Logic with transmission gates • Problem: • Non-restoring logic. • Traditional CMOS “rejuvenates” signals

12. Restoring Pass Transistor Logic

13. Circuit Families • Static CMOS • Ratioed Circuits • Cascode Voltage Switch Logic • Pass-transistor Circuits • Dynamic Circuits