Production Readiness Review

1. Production Readiness Review On behalf of: Sergey Barsuk, Dominique Breton, Olivier Callot, Daniel Charlet, Olivier Duarte, Beng Ky, Jacques Lefrançois, Frédéric Machefert, Patrick Robbe, Vanessa Tocut Ioana Videau.

2. The FE board in the FE crate. 264 boards including spares will be produced 6500 +1500 Channels In 14+4 ECAL & HCAL crates 366.7 mm 280mm 26 x ‘9U‘ Crates

3. L0 calorimeter trigger

4. A crate … almost full !

5. Calorimeter FE board.

6. Some details ADC FE_Pga Delay lines Serializers + Deserializers Analog chip Trig_PGA Delay chip Lemo (Probes) Seq_Pga APA connector Glue_Pga Analog input connectors Clock Receiver/drivers Rad-hard regulators Delatchers AX connector

7. Block diagram of the FE board.

8. Analog part. The set of resistors can be easily removed to match the variation on the input impedance of the ADC (+- 64 ADC count ) 10 meters ( same for all ) On-detector clipping Buffer Pedestal adjustment to ~128bins Delay line Cable effect cancellation

9. Delay Chip • Technology : AMS 0.8µm pure CMOS process in a 28 pin SOZ package • Production tested and recorded in a database: yield is about 95%. • The power consumption is about 40mA@3.3V. • The linearity is better than +/- 100ps per step. • The clock jitter is less than 15ps RMS for all channels. Needs to receive a reset after programming of a large step on the output delays.

10. Fe PGA Needs to be checked permanently. Added in the control word 3 modes for RAM advance Duty cycle of 50% ( FDR )

11. Triple voting FIFO (derandomizer)

12. ADC data processing Possibility to decrease the HV Clock adjustment study: next talk 2 methods for pedestal subtraction

13. Principles of ECAL/HCAL L0 Trigger Front-end boards y Calorimeter cells Crates Cable links between crates (16 bits serialized 280 MHz) – 2 Cables per card Backplane connections (40 MHz) z  x FePGA2 FePGA3 FePGA4 FePGA5 FePGA6 FePGA7 FePGA0 FePGA1

14. TrigPGA : block diagram The phase of the clock of the serializer comes from the trigpga (FDR) • I/O used 306 out of 317 : 266 inputs • 39 outputs • And 1 bidirectionnal

15. Internal view of data computing

16. Front-end PGAs. The serializer clock comes from SEQ

17. Processing and formatting Derandomizer FIFO : 1bit ‘ And ‘ of the 8 Fe + 1 bit for the Sequencer. 2 Bits of PS/SPD + Calibration pulse and its mask . . BX - Id L0 - Id Parity Calib Test Seq PRS/SPD PRS/SPD 20 19 18 17 16 15 8 7 0 Header Channel 0 Line 1 É Channel 4 Channel 8 Line i [ É ] ¯ Channel 31 Channel Parity Trailer (Vertical Parity ) 4x ( ( i - 1 ) modulo 8 ) + Separator int ( ( i Ğ 1 ) / 8 ) Separator Parity Trigger ECAL/HCAL Data ECAL/HCAL 20 19 12 11 0

18. Glue PGA Only calorimeter- specific block

19. Clock distribution Next talk FDR FDR FDR Next talk New design of the clock tree

20. Power distribution Fault is sent individually via a dedicated line to the CROC ( FDR ) Board Consumption : +5 V = 4A +3.3V = 2 A -5V = 1 A

21. Programming-debugging : JTAG Chain

22. Test Control Calibration • 3 Modes : • L0 advance • Clock advance • Calibration advance • Trigger data • Spy ram • Neighbours • Cables • L0data • Spy ram • Croc Calibration channelB L0

23. Final layout • Thickness : 2.4 mm. • 12 layers • Minimum isolation : 0.11mm • Via : width = 0.35 mm • Plating : Ni-Au for BGAs • 3062 components • 3581 nets • 15800 pins • ~10000 connections • 6072 vias • via/connection 0.64 • Manhathan < + .1 % Man theo

24. Some layers …

25. Production • After tendering, three companies have been selected and their offers thoroughly studied. • We visited all of them for a whole day each. • One of them has been chosen based on all the elements we had in hand: Laudren in Lorient. • We’re really satisfied with this company up to now. • They have produced all the boards until now, so they have an almost perfect knowledge of the product. • The PCB is produced in France with a Ni/Au coating, compatible with press-fit connectors and BGAs. • All the components have already been delivered at the manufacturer. • The production flow and the in-factory tests will be presented by Dominique.

26. In the wake of Final Design Review: answer to the referees. 2 Prototypes (mid September) Standalone Test. Two cards for a combined test (neighbours) and test with Validation Card (cable and backplane) Test at CPO. => Modifications. 2 new Prototypes (December 5th): same as for the 2 former prototypes 16 Boards (pre-series) Test at CPO to validate the acquisition chain and launch the production of the FEPGA 16 boards in a Crate ( Wow ! ) Test with Validation Board (half a crate) Aging of 8 good boards to validate the aging process. Milestones before production

27. Production planning • Week 13 : - beginning of production preparation at Laudren • Launching of the programation of the Actel AX (FePGA and TrigPGA): 4chips/hour, 12hours/day • -> Test of one chip of each type ASAP. • Week 16 : beginning of the cabling of the 80 first PCBs. • Launching of the production of the remaining PCBs by batch of 80. • Week 19 : reception of the first 16 boards. • Week 23 : reception of the left-over of the first batch of 80 boards. • Week 24 : beginning of delivery of the second batch with a frequency of 32 boards per week until end of week 28.