Outline

1. On Modeling and Sensitivity of Via Count in SOC Physical ImplementationKwangok Jeong (kjeong@vlsicad.ucsd.edu) Andrew B. Kahng (abk@cs.ucsd.edu) Hailong Yao (hailong@cs.ucsd.edu) VLSI CAD LABORATORY UCSD Nov. 24, 2008

2. Outline • Motivation • Review of Via Count Estimation • Key Parameters to Via Count • Taxonomy of Via Count Modeling Approaches • Verification of Model • Conclusion UCSD VLSI CAD Laboratory ISOCC-2008

3. Motivation • Via analysis and estimation are of great importance • Yield: via open, high-resistance fault = key defect types • Evaluating performance of existing routers • 32nm via rules • Evaluating new technologies or designs • 3D implementation needs (via density, …) • Previous work based on “Rent’s parameter” • In this work, we give taxonomy of via modeling and propose a new via count model for placed designs average pins per gate Rent’s parameter number of terminals Landman et al., 1971 number of components UCSD VLSI CAD Laboratory ISOCC-2008

4. Truncated binomial series in Davis’s model Review of Via Count Estimation • Uezono’s model (T. Uezono et al., ISQED, 2006.) • Heavily depends on wire length and track utilization l : estimated wirelength ut : track utilization • Up to 19% error in the experimental results • Questionable argument • Why does #via increase with decreasing Rent’s parameter? • Uezono’s model uses • Davis et al.’s wirelength distribution that has error in #net for length = 1 Correlation between the Rent’s parameter p and the number of vias (Uezono et al., ISQED06) UCSD VLSI CAD Laboratory ISOCC-2008

5. Key Parameters Affecting Via Count • Experimental setup • For N, k, p, U, M and Tech: use Rentian circuit generator (gnl [1]) • For F: use two different clock frequency for AES from opencores.org • For k (in real design): AES SP&R with different cell sets (whole vs. restricted) [1] D. Stroobandt, P. Verplaetse and J. V. Campenhout, "Generating Synthetic Benchmark Circuits for Evaluating CAD Tools", IEEE Trans. On Computer-Aided Design Of Integrated Circuits and Systems, (19)(9) (2000), pp. 1011-1022. UCSD VLSI CAD Laboratory ISOCC-2008

6. Sensitivity to Design Parameters(Rentian Circuits) • Observations • N   #vias  • k   #vias  • p   #vias  • U   #vias  • M   #vias  #vias vs. #instance (N), technology(Tech), #metal (M), and utilization (U) #vias vs. #pins per gate (k), and Rent’s parameter (p) Experimental results show #via increases even for small Rent’s parameters #points to be connected wirelength track utilization UCSD VLSI CAD Laboratory ISOCC-2008

7. Sensitivity to Design Parameters (Real Designs) • AES (~15K) core from opencores.org • Clock frequency (F): 50MHz and 400MHz (8X) • #pins per gate (k) • Large-k: use a full set of cells in the library • Small-k: use only INV, BUF, NAND2 and DFF • Wiring pitch (wp): original, half (2x tracks)  #vias increases by 4~11% k increases from 2.7 to 3.6  #vias increases by 44%  #vias decreases by 17% #via vs. pins per gate (k) and frequency (F) #via vs. wiring pitch (wp) UCSD VLSI CAD Laboratory ISOCC-2008

8. Summary of Sensitivities to Design Parameters Routing Congestion or Track Utilization UCSD VLSI CAD Laboratory ISOCC-2008

9. Via Count Estimation • Key ideas • #vias strongly depends on kN = total #pins • M1 layer generally not used for cell connections  all pins need V12 • If no design rules, all routes can be implemented with 1-tier (H/V) of routing layers  No detours and no additional vias  baseline of #vias • Congestion increases #vias UCSD VLSI CAD Laboratory ISOCC-2008

10. Model: • VL: baseline of #vias • Vcongestion: additional vias from routing congestion • VL calculation • H-BBOX model • #VIA12 = #pins ( ) • #VIA23 = #pins • V-BBOX • #VIA12 = #pins • #VIA23 = 2 x #pins • Vcongestion calculation Taxonomy of Via Modeling Approach (1) • Analytical method • Inputs: given N, k and p • Enable to estimate #vias prior to netlist • Netlist-based method • Inputs: extracted N, k and p • Parameters are extracted from netlist  better accuracy Aspect ratio of net’s bounding box < 1 (H-BBOX: 2kN) Aspect ratio of net’s bounding box > 1 (V-BBOX: 3kN) UCSD VLSI CAD Laboratory ISOCC-2008

11. S: Sum of SMT length T: Sum of available track length Taxonomy of Via Modeling Approach (2) • Placement-based method • Inputs: placed design  accurate wirelength estimation • Baseline of #vias (VL) • Construct Steiner minimum tree (SMT) • Assign SMT segments to 1-tier routing layer • Horizontal  M3, Vertical segments  M2 • Diagonal segments  converted to ‘L’ shape  M2 and M3 • Count #vias at each point • Average routing congestion • Large congestion requires more vias • Placement-based via count model UCSD VLSI CAD Laboratory ISOCC-2008

12. Model Fitting using Training Designs • Finding model coefficients • Initial guess: • : via count increase due to via blockages ~ 4 • : affects probability of via blockage  • Final model coefficients ( ) • Average 3.4% error Via blockage A via blockage can increase #vias by more than 4 UCSD VLSI CAD Laboratory ISOCC-2008

13. Model Accuracy on Industry Designs • We apply proposed placement-based via count model to designs from different technologies and different routers • Our model shows 8% error in average UCSD VLSI CAD Laboratory ISOCC-2008

14. Conclusion and Ongoing Work • Conclusion • We evaluate the sensitivities of design and technology parameters on via count • Propose a new accurate placement-based via count estimation model • Experimental results are promising • 3.4% error on training designs with various instance counts, pins per gate, number of metal layers and wiring pitches • 8% error on various industry designs from different technologies and routers • Ongoing work • Accurate wirelength estimation for analytical and netlist-based via count modeling • Feed into the development of improved routers • Ability to assess impact of varying design rules and/or different router runtime options UCSD VLSI CAD Laboratory ISOCC-2008