Assaf shacham keren bergman luca p carloni
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On the Design of a Photonic Network-on-Chip PowerPoint PPT Presentation


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Presented for HPCAN Session by : Millad Ghane. Assaf Shacham , Keren Bergman, Luca P. Carloni. On the Design of a Photonic Network-on-Chip. NOCS’07. Why NoC ?. Scaling Transistor Speed and Integrity Tighter Logic Power Dissipation Increasing Number of Cores per Chip

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On the Design of a Photonic Network-on-Chip

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Assaf shacham keren bergman luca p carloni

Presented for HPCAN Session by: Millad Ghane

AssafShacham, Keren Bergman, Luca P. Carloni

On the Design of a Photonic Network-on-Chip

NOCS’07


Why noc

Why NoC ?

  • Scaling Transistor Speed and Integrity

    • Tighter Logic

    • Power Dissipation

  • Increasing Number of Cores per Chip

    • Bottleneck: Global Intrachip Communications

      • Bandwidth

      • Power

  • Performance-per-watt


Why optic

Why Optic ?

  • Low Power Dissipation

  • Ultra-high Throughput

  • Minimal Latency

  • End-to-end Transmission

    • No Repeating

    • No Regeneration

    • No Buffering

A silicon ring resonator


Hybrid architecture

Hybrid Architecture

  • Photonic Interconnection

    • High Bandwidth Messages

  • Electronic Interconnection

    • Low Bandwidth Messages

    • Short Control Messages


Photonic properties

Photonic Properties

  • Advantages

    • Bit-rate Transparency

      • Not Switching by Every Bit of Data

      • Switching Once per Message

    • Low Loss in Optical Waveguide

      • Independence of Transmission Distance

  • Disadvantages

    • No Storage Element

    • E/O and O/E Conversions

      • Off-chip Lasers


Packet life

Packet Life

Optic Network

Electronic Network

D

D

S

Sending path-setup packet

S


Packet life1

Packet Life

D

D

S

Sending optical packet

S


Packet life2

Packet Life

D

D

S

Sending path-teardown packet

S


Packet life3

Packet Life

D

D

S

Sending path-blocked packet

S

path-teardown packet


Building blocks

Building Blocks

70 µm

Photonic Switching Element

70 µm

Electrical Router


Building blocks problems

Building Blocks Problems

  • No Injection/Ejection Port

  • Not Deadlock-Free

    • Wide Turns


Approach

Approach

Ejection Switch

Injection Switch

Gateway Switch

Torus Network Nodes

Access Points

Address Format


Deadlock solution

Deadlock Solution

  • Injection-Ejection Blocking

    • [previous slide]

  • Intra-dimentional Blocking (Torus Network)

    • Virtual Channel Flow Control

      • Circuit Switching

    • terminate-on-timeout packet


Simulation parameters

Simulation Parameters

  • POINTS Simulator

    • Based on OMNET++

  • 36-core CMP

    • 6x6 planar

  • Chip size: 20 x 20 mm

  • Uniform Traffic

  • 3 Cases

    • Deadlock

    • Message Size Optimization

    • Increasing Path Diversity

2


Message size optimization

Message Size Optimization

  • Long path-setup latency

    • Nonoseconds

  • Super fast transmission

Overhead Ratio:


Message size optimization cont

Message Size Optimization (cont.)

  • Message Duration: 50ns

  • Message Size: 2KB Suitable for DMA Trans


Increasing path diversity

Increasing Path Diversity

  • PD=2

    • Less Hardware

    • Less OverheadDifference


On the design of a photonic network on chip

Q & A ?

Thanks !


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