Network on chip router
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NETWORK ON CHIP ROUTER. PART A Midterm presentation. Students : Itzik Ben - shushanJonathan Silber Instructor : Isaschar Walter. Winter 2006. Problem: Power, size and performance not practical for multi-processor chips using a single bus interconnection. Solution:

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NETWORK ON CHIP ROUTER

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Network on chip router

NETWORK ON CHIP ROUTER

PART A

Midterm presentation

Students : Itzik Ben - shushanJonathan Silber

Instructor : Isaschar Walter

Winter 2006


Network on chip router

Problem:

Power, size and performance not practical for multi-processor chips using a single bus interconnection.

Solution:

Network on Chip, based interconnection:

fast, reliable data and low power consumption.


Project goals

Project Goals

  • Implement a router forNoCin VHDL

    based upon research made by faculty

    members.

  • Design and implement interface units between NoCrouters and process units.

  • Design and implement an application of multi processing units using a Network on Chip based interconnection.


Noc general schematic

Interface

Interface

Interface

Interface

ROUTER

ROUTER

ROUTER

ROUTER

ROUTER

ROUTER

Interface

Interface

Processing Unit

NoC General Schematic

NoC

Interface

Interface

ROUTER

ROUTER

ROUTER

Interface


Router 5x5

Input

Port

Output

Port

Router 5x5

Processing

Unit

ROUTER

Interface

North

West

Crossbar

Data

East

Control

Data

Control

South


Packets in wormhole architecture

Packets in Wormholearchitecture

  • Each Packet is divided to several flits

  • Each flit is several bits width

A whole Packet

Packet body

Target Address

Command


Interface

Process

Unit

Process

Unit

Process

Unit

Process

Unit

Process

Unit

Interface

Interface Between Bus & Router

Local

Bus

To Router

From Bus to Packets

Processing

Unit

Packets in Wormhole

architecture


Wormhole packets in service

Wormhole Packets in Service

Type :

Idle

FP

Body

EP

Data out

x N

flit

x 2

Type

SL :

Signaling

Real-Time

RD/WR

Block Transfer

Service Level

x 2


Router input port

FIFO

FIFO

CRT

CRT

Router Input Port

Current Routing Table

ROUTER

  • Input

  • Port

  • Crossbar

    Data Per

    Service-

    Level

    PREVIOUS ROUTER IN PATH

    Data In flits

    Switching SL

    Input Buffer

    Control

    Input Port

    Control

    Buffer credits


    Network on chip router

    Crossbar Example for 2 Service Levels

    From Input Port

    To Output port

    switch

    Round Robin

    To Output Port

    From Input Port

    CrossbarControl

    CRT+Type

    CSIP+NBS


    Router output port

    CSIP

    CSIP

    NBS

    NBS

    Router Output Port

    Currently Serviced Input Port

    Next Buffer State

    ROUTER

    • Output

  • Port

  • Crossbar

    Data Per

    Service-

    Level

    NEXT ROUTER IN PATH

    Data In flits

    Switching SL

    Control

    Output Port

    Control

    Buffer credits

    Buffer credits


    The router control

    The Router Control

    Inputs :

    • Type/SL – from flit data.

    • FIFO control lines.

    • CRT,NBS (from buffer credits) ,CSIP.


    Project schedule first semester goals

    Project schedule - First Semester Goals

    • Implement On Virtex II Pro, week 8 .

    • Operate peripherals on board, week 9. 

    • Operate PPC on board, week 10. 

    • Design an architecture of a simple router,

      week 11.

    • Implement and Simulate the router,

      weeks 12-13.

    • Debug of the router, week 14.


    Final goal part a

    Final GoalPart A

    • 3x3 Router

    • 2 Service Levels

    • Receiving/Transmitting

      A One Flit Packet (FP)


    Project schedule second semester goals

    Project schedule - Second Semester Goals

    • Adding Virtual-Channel to Router architecture .

    • Development of interface to the network

    • Final Goal :

      Implement a QNoC based application on

      a FPGA.


    Adding virtual channel

    FIFO

    FIFO

    FIFO

    FIFO

    FIFO

    FIFO

    CRT

    CRT

    CRT

    CRT

    CRT

    CRT

    PREVIOUS ROUTER IN PATH

    Input Buffer

    Adding Virtual Channel

    ROUTER

    • Input

  • Port

  • Crossbar

    Data Per

    Service-

    Level

    Switching SL

    Control

    Input Port

    Control

    Buffer credits


    Network on chip router

    THANK YOU


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