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NETWORK ON CHIP ROUTER. PART A Midterm presentation. Students : Itzik Ben - shushan Jonathan Silber Instructor : Isaschar Walter. Winter 2006. Problem: Power, size and performance not practical for multi-processor chips using a single bus interconnection. Solution:

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network on chip router

NETWORK ON CHIP ROUTER

PART A

Midterm presentation

Students : Itzik Ben - shushan Jonathan Silber

Instructor : Isaschar Walter

Winter 2006

slide2
Problem:

Power, size and performance not practical for multi-processor chips using a single bus interconnection.

Solution:

Network on Chip, based interconnection:

fast, reliable data and low power consumption.

project goals
Project Goals
  • Implement a router forNoCin VHDL

based upon research made by faculty

members.

  • Design and implement interface units between NoCrouters and process units.
  • Design and implement an application of multi processing units using a Network on Chip based interconnection.
noc general schematic

Interface

Interface

Interface

Interface

ROUTER

ROUTER

ROUTER

ROUTER

ROUTER

ROUTER

Interface

Interface

Processing Unit

NoC General Schematic

NoC

Interface

Interface

ROUTER

ROUTER

ROUTER

Interface

router 5x5

Input

Port

Output

Port

Router 5x5

Processing

Unit

ROUTER

Interface

North

West

Crossbar

Data

East

Control

Data

Control

South

packets in wormhole architecture
Packets in Wormholearchitecture
  • Each Packet is divided to several flits
  • Each flit is several bits width

A whole Packet

Packet body

Target Address

Command

interface

Process

Unit

Process

Unit

Process

Unit

Process

Unit

Process

Unit

Interface

Interface Between Bus & Router

Local

Bus

To Router

From Bus to Packets

Processing

Unit

Packets in Wormhole

architecture

wormhole packets in service
Wormhole Packets in Service

Type :

Idle

FP

Body

EP

Data out

x N

flit

x 2

Type

SL :

Signaling

Real-Time

RD/WR

Block Transfer

Service Level

x 2

router input port

FIFO

FIFO

CRT

CRT

Router Input Port

Current Routing Table

ROUTER

    • Input
  • Port

Crossbar

Data Per

Service-

Level

PREVIOUS ROUTER IN PATH

Data In flits

Switching SL

Input Buffer

Control

Input Port

Control

Buffer credits

slide10

Crossbar Example for 2 Service Levels

From Input Port

To Output port

switch

Round Robin

To Output Port

From Input Port

CrossbarControl

CRT+Type

CSIP+NBS

router output port

CSIP

CSIP

NBS

NBS

Router Output Port

Currently Serviced Input Port

Next Buffer State

ROUTER

    • Output
  • Port

Crossbar

Data Per

Service-

Level

NEXT ROUTER IN PATH

Data In flits

Switching SL

Control

Output Port

Control

Buffer credits

Buffer credits

the router control
The Router Control

Inputs :

  • Type/SL – from flit data.
  • FIFO control lines.
  • CRT,NBS (from buffer credits) ,CSIP.
project schedule first semester goals
Project schedule - First Semester Goals
  • Implement On Virtex II Pro, week 8 .
  • Operate peripherals on board, week 9. 
  • Operate PPC on board, week 10. 
  • Design an architecture of a simple router,

week 11.

  • Implement and Simulate the router,

weeks 12-13.

  • Debug of the router, week 14.
final goal part a
Final GoalPart A
  • 3x3 Router
  • 2 Service Levels
  • Receiving/Transmitting

A One Flit Packet (FP)

project schedule second semester goals
Project schedule - Second Semester Goals
  • Adding Virtual-Channel to Router architecture .
  • Development of interface to the network
  • Final Goal :

Implement a QNoC based application on

a FPGA.

adding virtual channel

FIFO

FIFO

FIFO

FIFO

FIFO

FIFO

CRT

CRT

CRT

CRT

CRT

CRT

PREVIOUS ROUTER IN PATH

Input Buffer

Adding Virtual Channel

ROUTER

    • Input
  • Port

Crossbar

Data Per

Service-

Level

Switching SL

Control

Input Port

Control

Buffer credits

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