PIXEL. H. Wieman HFT CDO LBNL 25-26-Feb-2008. topics. Pixel specifications and parameters Pixel silicon Pixel Readout STAR telescope tests Mechanical organization. Pixel geometry. End view. 8 cm radius. 20 cm. 2.5 cm radius. Inner layer Outer layer. coverage +-1.
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8 cm radius
2.5 cm radius
One of two half cylinders
total 40 ladders
pixel chips (MAPS) produced by
IReS/LEPSI IPHC (Strasbourg)
All sensor families:
Mimostar 2 => full functionality 1/25 reticule, 1.7 µs integration time (1 [email protected] MHz clk), analog output. (in hand and tested)
Phase-1 and Ultimate sensors => digital output (in development)
Data Processing in RDO and on chip by generation of sensor.
The RDO system design evolves with the sensor generation.
Phase 1 – Nov 2008
Ultimate – Nov 2009
Preliminary tests in Saclay of chips with 20 µm and 14 µm thick epitaxy layer
IHCP Marc Winter et al
R = 8.0
R = 2.5
Chip dimension: 4 mm X 4mm, 128 X 128 pixelsPrototype test in STAR with 3 Sensor Telescope
Our goal was to test functionality of a prototype MIMOSTAR2 detector in the environment at STAR in the 2006-2007 run at STAR. We obtained information on:
ladder data generator
6 m robust twisted pair cable
Virtex5 development board
DDL/SIU fiber link
42 fine gauge twisted pairs
Duplicate ~10 times for final system
Full self consistent spatial mapping prior to installation
Installation and removal does not disturb mapping
20 Micron stability
(mapping of BaBar with visual coordinate machine)
8 inch wafers
237 k$ incremental silicon cost for the 3 spare copies
Two board System – Virtex-5 Development board mated to a new HFT motherboard
Xilinx Virtex-5 Development Board
Note – This board is designed
for development and testing.
Not all features will be loaded