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2.7 NAND and NOR logic networks

2.7 NAND and NOR logic networks. Introduce the use of NAND and NOR gates in the synthesis of logic circuits Attractive due to their simpler electronic circuits implementation than AND and OR functions Q: Can be used directly in the synthesis of logic circuits? And how?.

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2.7 NAND and NOR logic networks

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  1. 2.7 NAND and NOR logic networks • Introduce the use of NAND and NOR gates in the synthesis of logic circuits • Attractive due to their simpler electronic circuits implementation than AND and OR functions • Q: Can be used directly in the synthesis of logic circuits? And how?

  2. Graphical symbols for NAND and NOR gates (Figure 2.20) • A bubble at the output side of the gate symbols • represents the complemented output signal.

  3. DeMorgan’s theorem in terms of logic gates x 1 x x 1 1 x x 2 2 x 2 (a) A NAND gate is equivalent to the OR gate with inversions at its inputs. x 1 x x 1 1 x x 2 2 x 2 (b) A NOR gate is equivalent to the AND gate with inversions at its inputs

  4. x x 1 1 x x 2 2 x x 3 3 x x 4 4 x x 5 5 x 1 x 2 x 3 x 4 x 5 1 Transform a AND-OR networks into a network of NAND gates • Replace each connection between AND and OR gate by inversions of signals. • Replace OR gate with inverted inputs by a NAND gate. Double inversion has no effect on the network behavior. 2 Same topology! Figure 2.22. Using NAND gates to implement a sum-of-products.

  5. x x 1 1 x x 2 2 x x 3 3 x x 4 4 x x 5 5 x 1 x 2 x 3 x 4 x 5 • Can implement any OR-AND network as a NOR-NOR network having the same topology with the similar transformation procedure. Figure 2.23. Using NOR gates to implement a product-of sums.

  6. Example 2.6 Combining property 14b. (x + y) (x + ) = x • Let us implement the function using NOR gates only = • The POS expression (x1 + x2 +x3) (x1+x2+)(+x2+) //apply combining property 14b to // M0 and M1; M1 and M5 =()

  7. x1 x2 f x3 (a) POS implementation in Example 2.4 x1 x2 f = x3 (b) NOR implementation Figure 2.24 NOR-gate realization of the function in Example 2.4.

  8. Example 2.7 Distributive property 12a. x (y + z) = xy + xz • Let us implement the function using NAND gates only • The SOP expression // merge m2, m3, m6, and m7 using P12a; // merge m4 and m6 = = x2+ All 4 combinations = 1

  9. x2= x2+x2 x2 x2 f x3 f x1 x1 x3 = (a) SOP implementation x2 f x1 x3 (b) NAND implementation Figure 2.25. NAND-gate realization of the function in Example 2.3.

  10. 2.8 Design Examples • Basic issues that a designer is always confronted with • Necessary to specify the desired behavior of the circuit. • The circuit has to be synthesized and implemented.

  11. Three-way light control • Let x1, x2, and x3 be the input variables that denote the state of each switch. • Assume that • the light is off if all switches are open • Closing any one of the switches will • turn the light on. • Closing a second switch will have to turn off the light, that is to say, light will be off if two (or no) switches are closed. • Turn the light on by closing the third switch if two switches are closed. Figure 2.26. Truth table for a three-way light control.

  12. Canonical SOP and POS • SOP expression for the specified function • POS expression for the specified function

  13. f x1 x2 x3 (a) Sum-of-products realization f1 x3 x2 f2 x1 f3 f f4 (a) Product-of-sums realization

  14. Multiplexer Distributive property 12a. x (y + z) = xy + xz • A circuit that generates an output that exactly reflects the state of one of a number of data inputs, based on the value of one or more selection control inputs. s x1 x2 f (s, x1, x2) f(s, x1, x2) = //12a = = = 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1

  15. Implementation of a 2-to-1 multiplexer = x 1 s x1 x2 f (s, x1, x2) f 0 0 0 0 s 0 0 1 0 x 2 0 1 0 1 f (s, x1, x2) s (b) Circuit 0 1 1 1 x1 0 1 0 0 0 x2 1 1 0 1 1 s 1 1 0 0 (d) More compact truth-table representation x 1 1 1 1 0 1 f x 1 2 (a) Truth table (c) Graphical symbol

  16. More about complex multiplexer • A 4-to-1 multiplexer has four data inputs and one output • Two selection control inputs are needed • A 8-to-1 multiplexer needs eight data inputs and three selection control inputs • Same circuit structure can be used to implement multiplexer using NAND gates. • More discussions on multiplexer are in Chapter 3 and 6.

  17. 2.12 Examples of Solved problems

  18. Example 2.8 Determine if the following equation is valid Solution: Derive a canonical SOP form for each expression (an algebraic approach) LHS = = ( 2 0 7 3 5 4 ) = RHS = = =

  19. Example 2.9 Combining property 14b. (x + y) (x + ) = x Determine the minimum-cost POS expression for the function f(x1,x2,x3,x4) = Solution: To find a POS expression we should start with the definition in terms of maxiterms, which is f = f = = (x1+x2+x3+) (x1+x2++) (+x2+x3+) (+x2++)(++x3+) = x1 + x2 +// combining property 14b = + x2 + = + x3 + f = (x1+x2+) (+x2+) (+x3+) = (x2+) (+x3+)

  20. Example 2.12 Combining 14a. xy+x = x Absorption 13a. x+xy = x Derive the simplest SOP expression for the function Solution: f = //consensus = // combining = = // absorption = Consensus 17a. xy + = xy+

  21. Problem 2.31 1 0 1 0 1 0 1 0 1 x 1 0 0 1 0 1 1 0 0 1 1 x 2 0 0 1 1 0 1 1 0 0 1 x 3 0 0 0 0 1 1 0 1 1 1 f 0 Time Figure P2.3. A timing diagram representing a logic function. Synthesize the function in the simplest SOP form

  22. Problem 2.31 1 x 1 0 1 0 1 1 0 0 1 0 1 x 2 0 0 1 1 0 0 1 0 1 1 x 3 0 0 1 0 1 0 1 1 0 1 f 0 1 0 0 1 1 0 0 1 Time The simplest SOP expression is x3+x1x2

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