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Large Scale Integrated Circuits. A Little History. In 1942, in the University of Pennsylvania's Moore School of Engineering, John Mauchly and J Presper Eckert built a machine to compute artillery firing tables for the Amercian government. . A Little History.

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Large Scale Integrated Circuits

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Large scale integrated circuits l.jpg

Large Scale Integrated Circuits


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A Little History

  • In 1942, in the University of Pennsylvania's Moore School of Engineering, John Mauchly and J Presper Eckert built a machine to compute artillery firing tables for the Amercian government.


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A Little History

  • This device weighing 30 tons and containing 100,000 electronic components, including 17,000 vacuum tubes, was called the Electronic Numerical Integrator and Computer (ENIAC).

  • This machine was 80 feet long and 18 feet high and utilized the decimal numbering system. Mauchly and Eckert also claimed that ENIAC was the first general-purpose electronic digital computer, but in 1973 this matter was settled by a US court, which declared that the Atanasoff-Berry computer was entitled to that honor.


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A Little History

  • Improvements continued until 1959, when both Jack Kilby, at Texas Insturments, and Robert Noyce, at Fairchild Semiconductor, discovered that resistors, capacitors and transistors could be made from a semiconductor material and that vast numbers of transistors could be etched onto a single silicon chip.

  • Thus, the age of integrated circuits had arrived, and from this point forward, computers continuously decreased in size and increased in power and performance.


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Transistor - a tiny electrically operated switch, or gate, that can alternate between “on” and “off” many millions of times per second

Microchips, Miniaturization, &MobilityFrom Vacuum Tubes to Transistors to Microchips

1940s vacuum tube towering over 1950s transistor


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Transistors

  • Replaced vacuum tubes

  • Smaller

  • Cheaper

  • Less heat dissipation

  • Solid State device

  • Made from Silicon (Sand)

  • Invented 1947 at Bell Labs


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Transistor Based Computers

  • Second generation machines

  • NCR & RCA produced small transistor machines

  • IBM 7000

  • DEC - 1957

    • Produced PDP-1


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Microelectronics

  • Literally - “small electronics”

  • A computer is made up of gates, memory cells and interconnections

  • These can be manufactured on a semiconductor

  • e.g. silicon wafer


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Generations of Computer

  • Vacuum tube - 1946-1957

  • Transistor - 1958-1964

  • Small scale integration - 1965

    • Up to 100 devices on a chip

  • Medium scale integration - to 1971

    • 100-3,000 devices on a chip

  • Large scale integration - 1971-1977

    • 3,000 - 100,000 devices on a chip

  • Very large scale integration - 1978 to date

    • 100,000 - 100,000,000 devices on a chip

  • Ultra large scale integration

    • Over 100,000,000 devices on a chip


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Memory


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Dr. Jay W. Forrester 

  • 1946-1951

    Dr. Forrester was director of MIT's Digital Computer Laboratory and was responsible for the design and construction of Whirlwind I, the first large scale, high-speed digital computer to go into complete operation. While working on computer technology, Dr. Forrester invented random-access, coincident-current magnetic storage, which was for many years the standard  memory device for digital computers.        

    This invention , which is called magnetic core memory, involved the phenomenon that when current flows through a core, the core becomes magnetized even the current is removed. The introduction of this kind of memory makes computers smaller in size, faster to access data, and more powerful. It also was what today's memory technology was based on.


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RAM

  • In 1970, the newly formed Intel company publicly released the 1103, the first DRAM (Dynamic Random Access Memory) chip (1K bit PMOS dynamic RAM ICs), and by 1972 it was the best selling semiconductor memory chip in the world, defeating magnetic core type memory.  The first commercially available computer using the 1103 was the HP 9800 series.


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RAM

  • Dr. Robert H. Dennard, a Fellow at the IBM Thomas J. Watson Research Center created the one-transistor DRAM in 1966. Dennard and his team were working on early field-effect transistors and integrated circuits, and his attention to memory chips came from seeing another team's research with thin-flim magnetic memory. Dennard claims he went home and within a few hours had gotten the basic ideas for the creation of DRAM. He worked on his ideas for a simpler memory cell that used only a single transistor and a small capacitor. IBM and Dennard were granted a patent for DRAM in 1968.


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RAM

  • RAM stands for random access memory, memory that can be accessed or written to randomly -- any byte or piece of memory can be used without accessing the other bytes or pieces of memory. There were two basic types of RAM, dynamic RAM (DRAM) and static RAM (SRAM). DRAM needs to be refreshed thousands of times per second. SRAM does not need to be refreshed, which makes it faster. Both types of RAM are volatile -- they lose their contents when the power is turned off. In 1970, Fairchild Corporation invented the first 256-k SRAM chip. Recently, several new types of RAM chips have been designed.


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RAM Basics

  • Similar to a microprocessor, a memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data.

  • The capacitor holds the bit of information -- a 0 or a 1 (see How Bits and Bytes Work for information on bits). The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state.


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RAM Basics Con’t

  • A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes empty.

  • Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and then writes it right back. This refresh operation happens automatically thousands of times per second.


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RAM Memory Cell


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Memory Modules

  • Memory chips in desktop computers originally used a pin configuration called dual inline package (DIP). This pin configuration could be soldered into holes on the computer's motherboard or plugged into a socket that was soldered on the motherboard. This method worked fine when computers typically operated on a couple of megabytes or less of RAM, but as the need for memory grew, the number of chips needing space on the motherboard increased.


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Memory Modules Con’t

  • The solution was to place the memory chips, along with all of the support components, on a separate printed circuit board (PCB) that could then be plugged into a special connector (memory bank) on the motherboard.


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RAM Examples


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Moore’s Law


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Moore’s Law

  • Gordon Moore made his famous observation in 1965, just four years after the first planar integrated circuit was discovered. The press called it "Moore's Law" and the name has stuck. In his original paper, Moore observed an exponential growth in the number of transistors per integrated circuit and predicted that this trend would continue. Through Intel's relentless technology advances, Moore's Law, the doubling of transistors every couple of years, has been maintained, and still holds true today. Intel expects that it will continue at least through the end of this decade.


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Moore’s Law

  • Increased density of components on chip

  • Gordon Moore - cofounder of Intel

  • Number of transistors on a chip will double every year

  • Since 1970’s development has slowed a little

    • Number of transistors doubles every 18 months

  • Cost of a chip has remained almost unchanged

  • Higher packing density means shorter electrical paths, giving higher performance

  • Smaller size gives increased flexibility

  • Reduced power and cooling requirements

  • Fewer interconnections increases reliability


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Moore’s Law


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Moore’s Law


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Chip Fabrication


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Steps in Manufacture of a Microchip

  • Make large drawing. Reduce drawing hundreds of times to microscopic size.

  • Duplicate reduced photo many times on sheet.


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Steps in Manufacture of a Microchip

  • Print sheet of multiple copies on a wafer made of silicon, a semiconductor.

  • Print layer after layer above and below original silicon surface.


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Steps in Manufacture of a Microchip

  • Cut wafer into chips.

  • Mount chip in frame with connective pins extruding.


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Miniaturization Miracles: Microchips, Microprocessors, & Micromachines

  • Types of microchips:

  • Memory

  • Logic

  • Communications

  • Graphics

  • Math

  • Microprocessor

  • Microcontroller


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Overview of Wafer Fabrication


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Overview of Wafer Fabrication

  • Four stages of Semiconductor Manufacturing

    • material prep

    • crystal growth and wafer prep

    • wafer fabrication

    • packaging

  • Wafer Fabrication

    • the series of processes used to create the semiconductor devices in/on the surface of the wafer


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Wafer Terminology

  • Chip, die, microcircuit, die,bar

    • the identical circuits covering the wafer

  • Scribe lines, saw lines, streets, avenues

    • small areas between the chips used to separate them

  • Engineering die, test die

    • special devices or circuits containing special chemicals to be tested during processing

  • Edge die

    • partial die patterns that will not function


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Wafer Terminology (cont.)

  • Wafer crystal plane

    • the crystal structure toward which the chip edges are oriented

  • Wafer Flats

    • the flatted edge which indicates the crystal structure and material type


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Basic Wafer Fab Operations

  • Layering

  • Patterning

  • Doping

  • Heat Treatments


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Layering

  • Adding thin layers to the wafer surface

    • either insulators, conductors or semiconductors

    • deposited by two major techniques - growing or deposition

  • Oxidation - growing a silicon dioxide layer on the wafer surface

  • Deposition - common techniques are CVD (chemical vapor deposition) Evaporation and Sputtering.


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Patterning

  • Series of steps resulting in removal of certain portions of the added surface layers

  • After removal a patternof the layeris left on the wafer surface.

  • Material removed may be in the form of a whole or just an island of material.

  • Patterning process known by names Litho, Masking, Photolithography, Photomasking, Microlithography

  • Patterning is the most critical basic operation.


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Patterning (cont)

  • Goal is to:

    • create circuit parts in the exact dimensions (feature size) required by the circuit design

    • locate them in their precise location on the wafer surface.

  • Errors in process or placement can change the electrical functions of the device.

  • Contamination can introduce serious defects that result in loss of good die.


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Doping

  • Places specific amounts of dopant in the wafer surface through openings in the surface layer.

  • Two techniques used are Ion Implantation and Thermal Diffusion.

  • Thermal diffusion - chemical process that takes place when wafer is heated to about 1000° C and exposed to vapors of the proper dopant.

  • Ion Implantation - physical process in which dopant atoms are ionized, accelerated to high speed and “shot” into the wafer surface


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Doping (cont)

  • Purpose:

    • create either N type or P type pockets in the wafer surface

    • these pockets form the PN junctions required for operation of the transistors, capacitors, diodes and resistors in the circuit


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Heat Treatment

  • Heat treatment to achieve specific results.

  • Annealing -

    • heat treatment (about 1000° C) occurring after ion implantation to repair disruptions in the wafer crystal structure.

  • Alloying -

    • occurs after metal conductor strips placed on wafer. Metal alloyed(about 450° C) to wafer surface to ensure good electrical conduction.


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Semiconductor ManufacturingProcess Steps

  • Hundreds of steps are often required in the wafer processing of an I.C.

  • The four basic operations are used repeatedly to build the parts of the device in and on the wafer.


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Building an MOS Transistor

  • Circuit Design

    • Block diagram of the circuit

    • Schematic

    • Circuit layout - using CAD of the composite (composite - the entire circuit including every layer)

    • The drawings are separated into layers and digitized (translating to a digital database)

    • Final drawing completed on a computerized X-Y plotter table


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Reticles and Mask

  • Reticle -a “hard copy” of the individual drawing recreated in a thin layer of chrome deposited on a glass or quartz plate.

  • May be used directly in the photo process or used to make a photo-mask or mask.

  • Masks are used to pattern a whole surface in one pattern transfer. Masks and reticles are similar in makeup.

  • Reticles and Masks are produced in a separate department or purchased from an out side vendor.

  • A Mask “set”is supplied for each type of circuit.


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Semiconductor Manufacturing

Wafer Fabrication Overview


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Wafer Fabrication Overview

  • Layering

  • Patterning

  • Doping

  • Heat Treatment


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Layering Operation

  • Thin layers of either conductor or insulator material are added to a wafer of silicon using one of two techniques.

  • Grown

    • Oxidation

    • Nitradation

  • Deposited

    • Chemical Vapor Deposition

    • Evaporation

    • Sputtering


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Patterning

  • Series of steps to remove oxide from a new layer to begin to form the circuit path.

  • These processes are known as Lithography, Masking or variations of those names.

  • The repeating of this process creates the surface parts of the device that make up the circuit.

  • A most critical operation - sets dimensions for device


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Doping

  • Process whereby specific amounts of dopant are embedded in the wafer through openings in the surface layers.

  • Thermal Diffussion and Ion Implant are two techniques commonly used to accomplish this.


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Heat treatment

  • Operations in which the wafer is heated and cooled to obtain two specific outcomes, “annealing” and “alloying”.

  • Annealing is the repair of a wafer’s crystal structure after ion implant has disrupted it.

  • Alloying is heat treating the wafer after metal deposition to ensure good electrical conduction.


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Layering Step 1

  • The Step - This first layer, called Field or Start Oxide, is a layer of silicon dioxide grown on a wafer through a process known as oxidation.

  • The Purpose - for protection and the creation of a doping barrier.

  • The Method - Thermally grown in a diffusion furnace.

  • The Illustration - Shows the new layer above the silicon substrate of a new wafer.


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1) Layering - field oxide


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Patterning Step 2

  • The Step - This pattern process leaves two holes in the field oxide known as source-drain holes

  • The Purpose - These holes define the source and drain areas of the transistor.

  • The Method - Photolithography, including masking process of spin, expose, develop of the pattern and etch to remove unwanted oxide.

  • The Illustration - shows the oxide removed to form the pattern.


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2) Patterning - source drain holes


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Doping Step 3

  • The Purpose -these “pockets” will form the P-N junctions required for the construction of diodes and transistors

  • The Step - creates two “N” type pockets in the wafer surface.

  • The Method - pockets formed through diffusion process and driven deeper through reoxidation

  • The Illustration - shows resultant “N”pockets (green) and new oxidation layer.


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3) Doping LayerN-type doping and reoxidation of source - drain


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Patterning Step 4

  • The Step - patterning is used to remove the field oxide in the gate region.

  • The Purpose - preparing the device for the construction of the gate region.

  • The Method - spin, expose, develop and etch to form the new region.

  • The Illustration - shows the material removed forming the gate region.


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4) PatterningGate region is formed


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Layering Step 5

  • The Step - exposed silicon in gate region and source and drain holes are reoxidized.

  • The Purpose - preparation for contact holes into source and drain regions.

  • The Method - thermal oxidation in a heating furnace.

  • The Illustration - the area above the source and drain regions shows oxide layer.


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5) LayeringGate oxide is grown


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Patterning Step 6

  • The Step - two holes are patterned in the reoxidized source and drain regions.

  • The Purpose - “contact” holes to connect the metalization layer to the source and drain regions.

  • The Method - spin, expose, develop and etch

  • The Illustration - shows the path opened to the source and drain regions.


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6) Patterning

Contact holes are patterned into source/drain regions


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Layering Step 7

  • The Step - deposition of a layer of metal across the entire surface of the wafer.

  • The Purpose - to provide a conduction path to the source, drain and gate regions.

  • The Method - low pressure chemical vapor deposition (LPCVD).

  • The Illustration - shows the metal layer overlaying the entire device.


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7) Layering

Conducting metal layer is deposited


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Patterning Step 8

  • The Step - patterning the wafer to define the circuit path.

  • the Purpose - removal of unwanted metal to reveal electrical path for circuit operation.

  • The Method - metal etch using high energy plasma generated in RF field.

  • The Illustration - the metal conduction layer shown in blue above the source, drain and gate regions.


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8) Patterning

Metal layer is patterned


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Heat Treatment (Alloy) Step 9

  • The Step - wafer is heated to alloy the metal to the exposed source and drain regions.

  • This Purpose - ensures good electrical contact.

  • The Method - annealing in a nitrogen gas atmosphere.

  • The Illustration - the device appears the same.


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9) Heat Treatment

Metal is alloyed to layer


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Layering Step 10

  • The Step - application of a passivating layer

  • The Purpose - to protect the wafer surface during testing and packaging.

  • The Method - a polyimide spin which includes a curing process in diffusion.

  • The Illustration - Shows the final protective layer.


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10) Layering

Protective passivation layer is deposited


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Pad Mask Step11

  • The Step - patterning process removing the passivating layer from over the terminal pads on the periphery of the chip.

  • The Purpose - to provide electrical to the chip through the passivation layer.

  • The Method - a more involved masking process to remove the unwanted polyimide.

  • The Illustration - the opening above the bond pad is shown.


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11) Patterning

Passivation layer is removed over metal pads


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Electrical Test and Sort

  • The Steps - wafer is electrically tested for each component of the process and sorted for speed and functionality

  • The Purpose - to determine if process is correct and functionality and speciifcations of each device.

  • The Method - electrical test and sort test each device on the wafer in a systematic method.


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Wafer Sort

  • Each chip is electrically tested for continuity and functionality

  • Wafer is mounted on a vacuum chuck and aligned to thin electrical probes that contact each bonding pad on the chip.

  • Wafer probers are automated so that after aligning with an automatic vision system to the first chip the entire sequence is completed without operator assistance.


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Wafer Sort (cont)

  • Goals of wafer sort

    • Identification of working chips before they go into packaging

    • Characterization of the electrical parameters of the device (engineering tracking of device performance)

    • Yield determination (good vs bad or non-functioning die) used for feedback to process engineering.

      • Bad die are usually marked with an ink dot or located on a computer map of the wafer.


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Packaging

  • Sorted wafers are then moved to packaging.

  • This may be off shore or in another part of the facility,

  • The wafers are sawn into chips with a diamond saw and the good die separated from the bad

  • The chips are them mounted into lead frames and die attached.

  • The bond pads are wired bonded and the package is finally sealed.


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