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Chapter 5

Chapter 5. PC computer family architecture. History. 1971 Intel Chip 4004 (a 4 bit cpu) 1975 I-8080 (an 8 bit general purpose cpu) 1977 - Altair 8800 TRS-80 and Commodore PET 1980 - Apple 1981 - IBM PC 8086. History. 8088 a cheaper version of 8086 PC-bus

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Chapter 5

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  1. Chapter 5 PC computer family architecture

  2. History • 1971 Intel Chip 4004 (a 4 bit cpu) • 1975 I-8080 (an 8 bit general purpose cpu) • 1977 - Altair 8800 TRS-80 and Commodore PET • 1980 - Apple • 1981 - IBM PC 8086

  3. History • 8088 a cheaper version of 8086 • PC-bus • used 8 bit data bus. 8bit expansion cards were cheaper. • Address bus had 20 bits addressing 1 meg • Open architecture contributed to its success • 1984 IBM AT - 80286

  4. IBM AT • same ISA as the PC • provided additional hardware support for memory segmentation and protection • Real mode - the 8088 compatibility mode • 16 bit I/O path • 24bit address bus path (giving 16 MB) • PC AT bus

  5. Display adapters • MDA 720x 350 • CGA (320 x 200) 4 colors • EGA (640 x 350) 16 colors

  6. PS/2 • 1987 - IBM’s attempt to monopolize PC market • Micro Channel Architecture • VGA (640 x 480) • models 25 and 30 - 8086 chips • models 50 and 60 - 80286 chips • model 80 - 80386 - full 32 bit MCA bus • Model 70 1988 - 386sx - with 16 bit data bus (lesser cost because they could use older motherboards, I/o boards and memory)

  7. 80486 • 1988 - included internal cache and a mathcoprocessor • XGA - extended graphics array 1024 x768 - 256 colors

  8. PC clones • Extended Industry Standard Architecture (EISA) • 32 bit

  9. Micro computer configuration • Motherboard • slots - daughter boards • Chip set • Coprocessors • Discuss this

  10. 8088 CPU-ISA • 8-bit and 16-bit unsigned binary integers • 8-bit and 16-bit two’s complement integers • Unpacked decimals. One BCD per byte. (high order bits are zeros) • 13 16-bit special-purpose registers and a set of 9 flags

  11. Registers • AX - accumulator BX - base register • CX - holds count during data transfer instructions • DX - holds temporary data • has four segment registers • uses segment register addressing • software can access these segments independently • SI - source index • DI destination index

  12. Instruction set • Instruction types • arithmetic (integer, decimal) • Shift and Rotate (with or without carry) • logical (and, or, xor, not) • string (move, compare, scan) • control transfer (jump, loop, repeat, call, return) • interrupt (initiate, return, set and clear if flag) • Stack (push, pop, push flags, pop flags)

  13. Instruction set • load, store, and exchange (byte or word) • processor control (escape, halt lock, test, wait, no op) • In and out (byte or word) • others - adjust, convert, and translate)

  14. Instruction format • op-code - one byte • Implied operand instructions only has op-code • Immediate data - one or two bytes • Instructions that access memory has several bytes for each address specification. • Each address specification consists of address-mode byte followed by one or two displacement bytes. • The CPU selects a segment register by default. A programmer may override it.

  15. Addressing • CPU computes the 20-bit effective address in two parts. • First, computes a 16-bit CPU address. • Second, it computes the effective address using segment register addressing. • Because 8088 does not support virtual memory the physical address is the same as the effective address. • During instruction fetch, the CPU gets the 16-bit CPU address of the instruction from the program counter (IP)

  16. Addressing • During stack access it gets the CPU address from the stack pointer. • During execution the CPU uses address mode byte and the displacement field of the instruction to determine the operand’s CPU address.

  17. Effective address formation • Segment register is used to convert the CPU address into 20-bit effective address. • The segment registers point to four 64-KB segment of the main memory called the data segment, code segment, stack segment, and extra segment (DS, CS, SS, ES) • Instruction fetch - uses IP, CS • Stack operation - SP, SS • Other operations defaults to the following, which the programmer may override: • BP, SS. DI, ES (string), DI,DS

  18. I/O • IN - receive from the port • OUT - send to port • CPU takes the port address either from the instruction itself as an immediate operand, or from DX

  19. Control interface • 8088 is housed in a 40 pin package • Pins are address, data, power and control • Several pins must do more than one function so used TDM • CPU sends only one byte at a time so a word will have to be split up

  20. CPU bus control • 80888 uses bus cycles that takes 4 clock cycles • CPU places address on bus • address is divided into 3 parts, bits 19-16, bits 15-8 and bits 7-0 • I/O bus cycle • the address selects a memory location or I/O device • Either reads or writes data • During read/write the CPU places the datum on pins AD7 to AD0 • The selected memory or the device accepts the data send by CPU or these devices places data on the bus for CPU to accept.

  21. Interrupt processing • CPU uses an interrupt controller, so external devices do not communicate directly with CPU • When an external device requests an interrupt, it sends the request to the interrupt controller which in turn requests the CPU for an interrupt.

  22. Interrupt processing • the CPU initiates a special sequence of bus cycles - interrupt-acknowledge sequence. • The external device then places its interrupt-vector number on the data bus. • CPU reads the vector number and uses it to find the offset for the interrupt vector table and branches to the appropriate interrupt handler.

  23. Intel 8259A interrupt controller • 8088 has only two interrupt-control inputs, non-maskable (NMI) interrupt and interrupt request (INTR) • When two devices asks for interrupts, an arbitration must be made. The 8259A does that.

  24. 8259A functions • receive interrupt requests from up to eight different sources • mask certain requests • prioritize requests • process the CPU’s interrupt acknowledge signals by sending the interrupt-vector number to the CPU.

  25. DMA controller • Using CPU to control I/O traffic would be an inefficient use of CPU time. • DMA takes care of • signaling the I/O device to transfer the next byte of data • the datum is transferred to the next memory location • Checks to see if any more data to transfer.

  26. Intel’s 8237 DMA controller • special purpose processor designed to transfer blocks of data between memory and I/o devices. • 8237 has four independent I/o channels (can control 4 data transfers at the same time) • During the data transfer, the DMA controller becomes the bus master, it generates the memory addresses and informs the I/o interface of when to place data onto or when to take the data from the bus.

  27. 8237 DMA • has 27 registers: 20 are channel specific (5 registers for each channel), the other 7 are system wide. • There are four transfer modes for DMA • DMA single mode - request the bus for each byte it wishes to transfer • DMA block mode - does not relinquish the bus until it finishes the whole block • DMA demand mode - DMA remains bus master as long as the attached device wants to. • DMA cascade, more than one DMA is involved

  28. DMA operation • Before a transfer beings CPU programs the transfer operation • it sends the base address, base count and transfer parameters to the desired channel in the DMA controller • The DMA controller automatically load the current-address and current count registers with base address and base count. • The CPU prepares the device with OUT instructions. • Activates DMA controller by clearing the channel’s mask bit.

  29. I/O channel bus • this was the assignment you did. • if you do not remember please read starting with page 257.

  30. I/O system • Two i/o instructions, IN, OUT • When executing IN instruction, the C PU initiates and I/O read cycle • Either the instruction or the DX register holds the I/O port address • The CPU places that address on the address bus • The device places the data on the data bus, CPU reads it and puts it in the AL register • When issuing and OUT instruction, the CPU places the address of the device on the address bus and the data on the data bus. The addressed device accepts the data.

  31. I/O interface adapters • Both parallel and serial I/O devices are supported. • serial transmits one bit at a time, while parallel transmit or or more bytes at a time. • 8255A, programmable parallel interface is used mostly printers • 8250 UART is used for serial i/o. (universal asynchronous receiver trasmitter) • Each i/o interface must have its own address decoding circuitry for determining its i/o port address.

  32. 8255 PPI modes of operation • Basic i/o o the default mode • strobed mode • bidirectional bus mode

  33. Serial I/O • UART is used to convert parallel data to serial data & vice versa. • 8250 UART is the chip that is used • Serial transmission • the sending device sends a true (higher voltage) on the transmission line when it is idle • A transmission begins when the line signal is changed to false (lower voltage) • After that each individual bit is send by sending higher or lower voltage for a fixed period of time

  34. Serial transmission contd. • A lower voltage is used for 0 bit and higher for 1 bit • The transmission rage, baudrate, specifies the number of changes in voltage per second. • The first bit that is sent after transmission begins is a mark bit (start bit) -lower voltage • following the start bit fixed number of data bits are sent • Then a parity bit is sent. Parity bit will depend on pre-configured options. • Terminates a character with a stop bit.

  35. Serial transmission contd. • In this type of transmission, the sending and receiving computer clocks do not have to be synchronized. So it is called asynchronous transmission. • The bit time is regulated by the transmitter and the receiver independently (receiver clock and transmitter clock)

  36. Errors • Overrun error • sending device continues to send data while the receiver is not ready • framing error • differences in the clock frequencies will cause the receiver to sample the transmission line at an inappropriate time. (Most appropriate time is in the middle of each bit). • parity error • bit errors during transmission due interference

  37. UART 8250 • To the UART what is usually attached is a modem • Modem converts digital voltage to analog tone and vice versa • 8250 has 8 control signal lines and eight handshake lines, all or not used. • skip the operation.

  38. Programmable interval timer • application devices needs time signals (for example memory needs refreshing) • Timer used in a PC is 8253 programmable interval timer • 8253 has 3 counters, channels 0,1,2 • Each channel has its own clock signal input, and two registers. • A counter starts with a count in the initial-count-register, with each clock tick the counter is decremented until it reaches zero. • The other register is used to indicate he mode of operation.

  39. Programming timer • writing values into three initial-count registers and 3 mode registers. • The DRM chips are refreshed every 2 ms. This is done in cooperation with the DMA controller. Each 128 memory locations are refreshed simultaneously, then the next and the next until all of the DRAM is refreshed. Then starts all over again.

  40. Floating-point Coprocessor • 8087 math coprocessor • if a mathco is not present software is used to simulate it. • 8087 has its own instruction set and registers

  41. ROM-BIOS • contains system initialization program • provide uses with support for performing I/O

  42. System initialization • Check reliability of hardware system • test first 16KB or RAM • test processor flags • test ROM containing BIOS • test timer • Check and program programmable devices • program the timer and DMA controller to refresh DRAM • test and initialize interrupt controller and video controller • test keyboard and diskette controller • load OS and transfer control to it.

  43. Conventional memory • storage locations that CPU can reference directly (220) • Conventional memory is divided into blocks • Largest block 0-640K is the program memory • 640-1024 block is reserved memory (upper memory or extended memory) • Upper memory is for ROM BIOS and other system components • See next slide for examples, or Table 5.6 for complete listing

  44. Reserved memory • 640-704 EGA or VGA • 704-720 MDA • 736-752 CGA • 960-1024 ROM BIOS

  45. Expanded Memory LIM 3.2 • Lotus, Intel and Microsoft (LIM) introduced EMS (expanded memory specification) • Uses 64K (816 to 880K) of reserved conventional memory to expand memory to 16megabyte • This 64 K is used to address additional memory

  46. Enhanced Expanded memory LIM 4.0 • Supports up to 32MB • more flexible address-mapping technique

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