NOVEL PROCESSES FOR SOI-BASED MEMS AT VTT

1. NOVEL PROCESSES FOR SOI-BASED MEMS AT VTT James Dekker, ack. Jaakko Saarilahti, Jyrki Kiihimäki, Hannu Kattelus

2. OUTLINE • Introduction • Ultrasonic transducers from polysilicon • The Plug-Up process • SOI Resonators • variations • Amorphous metals

3. INTRODUCTION • Different micromachining technologies: • Surface Micromachining • polysilicon and metal layers • oxide as sacrificial layer • Example:Acoustic emission sensor • Bulk Micromachining • anisotropic etching (TMAH) • SOI-based Micromachining • ICP etching • Buried oxide sacrificial layer • Example :Resonators Both surface and SOI processes benefit from a novel release etch procedure used at VTT

4. CAPACITIVE MICROMACHINED ULTRASONIC TRANSUCER (CMUT) • A device for detecting ultrasonic pressure waves (6 to 13 MHz) • NDT and ultrasonic imaging • Surface micromachined using polysilicon • Fully functional 500 element CMUT matrix has been demonstrated (1 mm2) • A Novel method for etching of the sacrificial layer has been used.

5. CMUT PROCESS BEGIN • Process begins with LTO+poly + 600 nm TEOS depositions • Deposition and patterning of nitride • Deposition of porous poly-Si • Cavity formed by HF etch and SC drying, then sealed with poly Si • More depositions and patterning to get final structure END

6. RELEASE ETCHING OF THE CMUT MEMBRANE Removing the sacrificial oxide with HF D = 40 - 60 um

7. CHARACTERIZATION OF RESONANCE • Q= 100 • PULL-IN VOLTAGE ~40-200 V

8. Resonators for RF applications require high Q values with low power consumption. Low phase noise (Quartz resonators are ~-150 dBc/Hz) Bulk acoustic mode offers excellent characteristics compared to flexural mode 12 MHz BAW 13 MHz Lame gap=1 um (mask) by ICP ~400 um LAME AND BAW RESONATORS from SOI BAW LAMÉ

9. RESONATOR PROCESSING • All MEMS processing is CMOS compatible • 5-10 um SOI, 1 um BOX • pattern metal • ICP etch resonator and gaps • HF release etch • Supercritical drying • Non-IC processing (esp. metals) done at back-end

10. CHARACTERIZATION • Measurement of S-parameters and resonance frequencies • Phase noise (-115 dBc/Hz at 1 kHz offset) 100 Hz Q>100 000 Q=180 000

11. ALTERNATIVE SOI-PROCESS FOR RELEASING LARGE STRUCTURES Plug-Up process Pattern and etch release holes, strip, line with poly Conventional process Nitride Etch cavity in HF and SC Dry Thin Poly-Si Fill with poly, etchback, repattern, etch gaps to release structure Poly-Si • Gaps and release holes by ICP etching • Structure released by HF etch followed by SC drying • suitable for small or rigid structures Better yield for large structures No holes in structure

12. MEMS first? IC first? Topography! Metallurgy! Complexity! MEMS, Amorphous Metals, and IC integration

13. Reactive co-Sputtering of Mo-Si-N DC C: Mo34Si20N41 (O5) 5.3 g/cm3 0.75 mWcm B: Mo19Si26N49 (O6) 4.2 g/cm3 4.8 mWcm Mo Si Wafers Ar N Target 2 Shutter

14. 80 RT 500 600 700 ) 60 W 900 1000 40 Sheet Resistance ( as-deposited 20 1100 0 20 40 60 80 100 120 140 160 180 200 o Temperature ( C) Thermal Stability 200 nm Mo-Si-N layers 800 Dark-Field 1000C / 1min in Ar Conductive MoN or MoSi precipitates ?

15. O+ O+ O+ O+ O+ Photoresist Microelectromechanical test device: variable capacitor • Sputter MoSiN onto resist • Dice • O2 plasma “release etch”

16. Conclusions • Amorphous metallic alloys are interesting alternatives for silicon in fabricating MEMS devices • Polymeric materials can be used for sacrificial layers • Stress is more uniform and controllable than for polycrystalline metals • Mo-Si-N is an IC-compatible material candidate • Low deposition temperature (down to room temperature) • High thermal stability

17. Summary • Surface and SOI-based micromachining are dominant processes at VTT • New release technology facilitates the fabrication of complex structures • Amorphous metallic alloys are interesting alternatives for silicon in fabricating MEMS devices