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FEE and DAQ for R3B Si Tracker

FEE and DAQ for R3B Si Tracker. Ian Lazarus. Overview of talk: R3B Si Tracker design philosophy Proposals for Implementation Impact of proposals on other R3B FEE/DAQ Status of project in UK. R3B Si Tracker will conform to the NUSTAR DAQ Principles: 3 interfaces or “docking stations”

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FEE and DAQ for R3B Si Tracker

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  1. FEE and DAQ for R3B Si Tracker Ian Lazarus

  2. Overview of talk: • R3B Si Tracker design philosophy • Proposals for Implementation • Impact of proposals on other R3B FEE/DAQ • Status of project in UK

  3. R3B Si Tracker will conform to the NUSTAR DAQ Principles: • 3 interfaces or “docking stations” • Timestamp • Slow Control • DAQ

  4. R3B Si Tracker FEE/DAQ philosophy • Use timestamps, not hard-wired triggers (in or out) Why? • Eliminating trigger connections removes cable reliability problems and grounding/isolation problems between sub-systems. • Adds possibilities when making software triggers e.g. to look back in time • Reduces or eliminates dead time (but not pileup) • Modularity- Why? • Easier to maintain and upgrade. • Easier to re-use (e.g. EXL). • Front end ASICs Why? • Large channel count- need to minimise electronics size, power. • reduce connections • buffer data as close to detectors as possible to improve SNR.

  5. R3B Si Tracker FEE and DAQOutline spec: • Caveat- Si not yet fully simulated so all numbers are provisional based on initial design proposal: • 100k channels of Si • ASICs and Si mounted on ladders • Cables from ASICs to FEE card • FEE cards handle about 16 ASICs (each ASIC 64 channels) = 1024

  6. Si Ladder ASIC R3B conceptual design for Si tracker FEE and DAQ Draft 1 April 2008 DSSD ASIC NUSTAR DABC DAQ FEE Card Handles 16 ASICs, each 64ch = 1024ch. Total approx 100 FEE cards Gbit Ethernet fibre(s) R3B input code module Slow Control Fibre Ethernet either fibre or HDMI links BUTIS BUTIS Fan-out fibre links

  7. R3B Si Tracker ASIC Proposal Shaper Pk Hold Mux PreAmp TFA Discr. • ASIC features: • Time Stamp • Zero Suppress • On chip ADC x64 Shaper Pk Hold PreAmp TFA Discr. Time Stamp Control ADC 12 bit 1MHz Buffer and Serial Readout

  8. R3B FEE card proposal BUTIS TS interface FPGA Read ASICs Merge data Buffer data Time Stamp Control I2C for ASIC control DAQ Readout Driver h/w 16 ASIC serial inputs Slow control Ethernet TS clock, & ctrl I2C ASIC control

  9. Data Time-Line T= 0 T= 50ns T= 4us T = 7 us T = 8us T= 15us Pulse triggers discriminator after approx 50ns. Data tagged with TS Real-time Data- timing controlled by analogue shaping. Liable to pileup losses. Shaper reaches peak after 1 to 4us (variable) Pk hold waits for Mux connection to ADC 0 to 64us (typ 3us) Buffered Data- timing controlled by memory size and processing rate. No losses if dimensioned right ADC value and TS written to buffer in ASIC FPGA reads and buffers all ASIC data

  10. Impact of proposals on other R3B FEE/DAQ • No hardware cross triggering. • Use time stamps and software triggering • There is no easy way to get access to discriminators inside the Si ASICs to make a timing start/stop signal- much easier to use time stamps. (Making a time-aligned 100,000 channel analogue multiplicity or logic OR is non-trivial) • For sub-TS ToF: if necessary, can add TAC to ASIC, measuring from discriminator to next TS clock pulse for fine timing. (Some or all channels?)

  11. R3B Si Tracker ASIC Proposal Shaper Pk Hold Mux PreAmp TFA Discr. TAC • ASIC features: • Time Stamp • Zero Suppress • On chip ADC • TACs? x64 Shaper Pk Hold PreAmp TFA Discr. TAC Time Stamp Control ADC 12 bit 1MHz Buffer and Serial Readout

  12. Impact of proposals on other R3B FEE/DAQ • Rate reduction. • Ideally, don’t do it; design FEE for full data rate and DAQ to process it all. (If we can afford it!) • Optionally could buffer data in FEE (or DAQ input stage) and select data for collection using TS range (typically based on TS from beam trackers or beam timing). c.f. GREAT software trigger. • Make accept/reject decisions based on full data in DAQ, not subsystems or FEE cards with partial data. • Implication is that other sub-systems should also follow the time stamped DAQ philosophy.

  13. Status of work in UK • Funding. • Money for R3B has been approved but has not yet been allocated- money has been promised but we can’t spend it yet. • Work • Most of 2008 spent defending grant, little real work • The first step will be full simulations of the Si to be sure that we design the DAQ and ASIC to match the real final system geometry and channel count. • Work done already on AIDA FEE (DeSpec)- final PCB routing now- so can benefit from that experience (64 channels from 4x 16ch ASIC per V5FX FPGA) • Ready to start design as soon as money appears.

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