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Trigger/Timing Logic Unit (TLU) for AIDA Beam-Test. David Cussans, AIDA Kick-Off, February 2011. Outline. Exiting EUDET JRA1 TLU Aims for Mini-AIDA-TLU (mTLU) Specification Schedule Cost Aims for AIDA-TLU (aTLU) Use of aTLU as Beam-Interface (BIF) Summary. EUDET JRA1 TLU.

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trigger timing logic unit tlu for aida beam test
Trigger/Timing Logic Unit (TLU)

for AIDA Beam-Test

David Cussans, AIDA Kick-Off, February 2011

outline
Outline

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Exiting EUDET JRA1 TLU
  • Aims for Mini-AIDA-TLU (mTLU)
    • Specification
    • Schedule
    • Cost
  • Aims for AIDA-TLU (aTLU)
  • Use of aTLU as Beam-Interface (BIF)
  • Summary
eudet jra1 tlu
EUDET JRA1 TLU

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Designed to give a simple but flexible interface to trigger/timing signals at EUDET JRA1 beam-telescope
  • Produces triggers from beam scintillators.
  • EUDET-Memo-2009-4
jra1 tlu interface
JRA1 TLU Interface

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Different triggering modes:
    • No handshake (trigger pulses high)
    • Trigger-Busy handshake
    • Trigger Data handshake
jra1 tlu interface1
JRA1 TLU Interface

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Triggers can be vetoed by DUT raising TRIGGER_CLOCK line.
    • Can be combined with simple trigger/busy handshake for “dead-time free” readouts that send a continuous stream of data.
    • Send “buffer almost full” signal.
  • Time-stamp stored for each trigger.
aida tlu
AIDA TLU

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Existing EUDET will continue to work and have compatible DUT interface.
  • Need a new TLU
    • Increased trigger rate: Move to one-trigger-per-particle for LHC detectors.
    • FPGA system available for lifetime of AIDA
    • Cheaper to produce TLUs for integration in home labs.
aida mini tlu mtlu
AIDA Mini-TLU (mTLU)

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Want to produce a prototype to test out ideas
  • This mini-TLU will be cheaper and easier to produce than existing TLU
  • Use new connector standard (FMC), increase lifetime.
    • Enthusiastically adopted by CERN: 11 FMC projects already
aida mtlu specification
AIDA mTLU specification

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Double-Width FMC with single LPC connector.
    • Use e.g. Xilinx SP601 to host.

75mm

139mm

aida mtlu front panel
AIDA mTLU Front Panel

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Four PMT inputs (Lemo-00)
  • One clock I/O (2-pole Lemo-00)
  • One GPIO (Lemo-00)
  • Two DUT (HDMI)
aida mtlu interface
AIDA mTLU Interface

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Four PMT Inputs (Lemo-00)
    • Use ADCMP551 fast comparator. <1ns propagation, ~ 100ps dispersion with amplitude. Threshold by DAC. +/-5V range.
  • Two DUT interfaces (HDMI)
    • Wanted to use RJ45 (compatibility), but won\'t fit on FMC
    • “Dongles” for conversion to LVDS/RJ45 or TTL/LEMO
aida mtlu interface1
AIDA mTLU Interface

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Use clock circuitry inside FPGA to receive or generate clocks.
  • Communication to DAQ by Gigabit Ethernet
    • Use “IPBus” firmware developed for LHC.
    • Will need a host to convert packets into EUDAQ format, but could be main DAQ PC
versions of mtlu
Versions of mTLU

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Different levels of build
    • Assembled into box ( “beam-test ready”)
    • Assembled onto metal plate ( “IKEA”)
      • Approximate cost ~ €1000 each.
    • FMC only - provide own FPGA ( “Aldi” )
    • Manufacture own from design files
  • Aiming for hardware ~ April 2011
beam interface prototype
Beam Interface Prototype

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Requirement for CALICE beam-interface (BIF) for beam-test.
  • Can use mTLU as prototype BIF
    • HDMI connector physically compatible with DIF-LDA link.
  • Full aTLU as a BIF
  • Hardware should work – but BIF-specific firmware needed.
full aida tlu
Full AIDA TLU

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Approximate specification:
    • Twelve PMT inputs
    • Six DUT inputs
    • Low jitter clock generation
  • Will need FPGA board with FMC-HPC (high pin count) connector.
  • Firmware almost identical to mTLU.
summary
Summary

David Cussans, AIDA Kick-Off, 16-19 Feb 2011

  • Work under-way to produce a AIDA mini-TLU
    • Aiming for early release
    • Low(er) cost way of integrating to EUDAQ at home lab.
  • Fully specify aTLU in light of mTLU experience
  • Can use same hardware (and probably most of the firmware) as a Beam-Interface (BIF)
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