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DAQ for KEK beam test. M.Yoshida (Osaka Univ.). Components. VLPC readout Stand Alone Sequencer (SASeq) Slow < 100Hz Buffering VLPC data with VME interface Fast > 10kHz expected TOF counter readout CAMAC ADC/TDC in KEK elec. Pool Readout via VME with VME-CCP interface module

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daq for kek beam test

DAQ for KEK beam test

M.Yoshida (Osaka Univ.)

components
Components
  • VLPC readout
    • Stand Alone Sequencer (SASeq)
      • Slow < 100Hz
    • Buffering VLPC data with VME interface
      • Fast > 10kHz expected
  • TOF counter readout
    • CAMAC ADC/TDC in KEK elec. Pool
    • Readout via VME with VME-CCP interface module
      • CCP : max 10 MByte/sec
  • DAQ software
    • UniDAQ developed by KEK
    • Running on Linux
    • Server (Evbuilder) + Clients (Collectors)
    • Already installed in PC at D0 test stand
    • Need to write collectors

ethernet

EvBuilder

CAMAC

VME

TKO?

VLPC

Collector

TOF

Collector

The other

Detectors

system overview
System Overview

Linux PC

VLPC backplane

VME BUS

6U

AFE II (L)

8x64 ch

PCI-VME

VLPC Cassette #1

Slow Control

1553

1024 ch

AFE II (R)

8x64 ch

SASeq #1

AFE II Control

8x64 ch

AFE II (L)

SASeq #2

VLPC Cassette #2

CAMAC-VME

1024 ch

AFE II (R)

8x64 ch

LVDS-VME #1

VLPC Cryostat

LVDS-VME #2

Serialized ADC DATA

LVDS-VME #3

CAMAC crate

LVDS-VME #4

4x8bit = 32 bit / board

lvds vme
LVDS  VME
  • MCM puts serialized ADC data
    • Need to deserialize before FIFO
  • Solution 1:
    • Custom-made VME board
      • [MCM  serialize]  cable  [deserialize  FIFO]  VMEbus
    • Under development in Fermilab
  • Solution 2:
    • Use KEK-FIFO board
      • 32-bit inputs / board
      • [MCM  serialize]  cable  [deserialize]  cable  [FIFO board]  VMEbus
    • Under development decoder board to deserialize ADC data
d0 fifo board
D0 FIFO board
  • Newly-designed by fermilab
  • Need to design
    • VME interface
    • FPGA program

FIFO/SRAM

FPGA

VME interface

VME bus

128-p metric conn.

AMP 1-352272-1

3:21 LVDS receiver (66MHz)

SN65LVDS96

kek fifo board gnv 100
KEK FIFO board(GNV-100)
  • Already exist / debugged
  • Standard VME 6U module
  • NIM ext. clock input
  • NIM trigger input
  • TTL 2x 16 bit data input
  • Operation in 100MHz
  • Depth: 65K x 32 bits
    • FIFO: IDT72V36100
  • Need LVDS decoder
lvds ttl module deserialize
LVDS-TTL module(deserialize)
  • Need +5/-5V power supply
    • Standard VME 6U board
  • 2x 8-pin deferential LVDS inputs
  • 2x 16 bit TTL outputs
  • NIM clock out

NIM CLOCK OUT

CLKOUT

A0-A2

D0-D7

CLKIN

D10-D17

NIM CLOCK OUT

CLKOUT

CN-34P

A0-A2

D0-D7

CLKIN

D10-D17

NIM CLOCK OUT

CN-34P

3:21 LVDS receiver (66MHz)

SN65LVDS96

DS90CR216A

RJ-48

summary
Summary
  • Started to design DAQ system for KEK beam test in the summer of 2005
  • Buffer module for VLPC data is under development to increase DAQ rate up to 10 kHz
    • D0 FIFO module
    • KEK FIFO module + decoder board
  • DAQ test / preparation in Nov. and Dec.
    • The completed system will be sent to KEK
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