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SRS Trigger Processor Option Status and Plans

SRS Trigger Processor Option Status and Plans. Sorin Martoiu (IFIN-HH). ATCA-SRS Status. First systems delivered IFIN-HH UPV and CERN (MAMMA Group) Beta firmware released New firmware will be released soon Integration with software under way. SRS ATCA card overview.

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SRS Trigger Processor Option Status and Plans

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  1. SRS Trigger Processor OptionStatus and Plans Sorin Martoiu (IFIN-HH)

  2. ATCA-SRS Status • First systems delivered • IFIN-HH • UPV and • CERN (MAMMA Group) • Beta firmware released • New firmware will be released soon • Integration with software under way

  3. SRS ATCA card overview Blade main board: 2 x Virtex 6 FPGA (LX130/240) 2 x DDR3 2 x mezzanine ports RTM I/O card: 2 x 8 SFP+ ports 2 x Rj45 (DTCC) 2 x NIM (SMA) ATCA Zone 3 RTM connector 2 x Mezzanines RTM I/O card v2: (under design) 2 x 10GbE (SFP+) 2 x 4 SFP+ ports 2 x Rj45 (DTCC) 2 x NIM (SMA) ATCA Zone 2 backplane connectors ATCA zone 1 power connector

  4. ATCA-SRS Specifications Rear Transition Module • Optional connection to outside world • 2 x 8 GTX (2 x 40(50)Gbps) • Ethernet, Infiniband, Slink,… • 2 x 10 GbE + 4 x SFP+ under design • 2 x DTCC link (4xLVDS - RD51 specific data, trigger, clock and control link) Full-mesh backplane connectivity • Board-to-board connections • 14 x 8 LVDS (13 x 9,6 Gbps – low latency)) Hub Backplane Connection (CH0) • 4 x GTX versatile connection • 2 x each FPGA • 4 x 1 (Master) FPGA • Custom protocol (eg. HS-DTCC), 10GbE, Infiniband, … • 40 GbE possible with V7 upgrade

  5. Low Latency LinksMezzanine Interface • 8 Samtec QTE/QSE Connector Samtec QTE/QSE Connector Power: 2.5V 3.3V 12V • 50 LVDS I/O • 16 SE • 2 LVDS CLKS (from PLL) 8 GTX Management

  6. Low Latency LinksOverview Mezzanine interface • 50 x LVDS • 8 x GTX Inter-FPGA link • 8 x LVDS (upgradable) • 2 x GTX Mezzanine interface • 50 x LVDS • 8 x GTX Full-mesh backplane connectivity • Board-to-board connections • 14 x 8 LVDS

  7. Low Latency LinksTimings Mezzanine interface • 50 x LVDS ~ 3 ns (eg. 320 MHz) Inter-FPGA link • 8 x LVDS (upgradable) ~ 15 ns (using SelectIO circuitry) Mezzanine interface • 50 x LVDS ~ 3 ns Full-mesh backplane connectivity • 15 x 8 LVDS ~ 15 ns (using SelectIO circuitry) *Measurements under way at IFIN-HH

  8. ATCA-SRS Upgrade Path • EicSysGmbh is already working on an upgrade design driven by RD51 members applications (deadline Sept.-Oct. 14) • Discussions with Eicsys on going regarding NSW application • Two possible upgrade scenarios for NSW Trigger Processor application: • A) Replace V6 on blade with V7 • B) Put V7 on mezzanine and upgrade V6 on blade to K7 or a smaller V7

  9. ATCA-SRS Trigger Processor K7/V7 – combine sTGC/MM results + Monitoring, Management, etc,. V7 – Track finding algorithm & combine results + V7 – Track finding algorithm OPTO OPTO OPTO OPTO To Sector Logic To Sector Logic (V7) FPGA OPO OPO OPO OPO (V7) FPGA (V7) FPGA (V7) FPGA OPTO OPTO OPTO OPTO OPTO OPTO OPTO OPTO MEZZANINE MEZZANINE MEZZANINE MEZZANINE Track results To/from neighbor card Track results To/from neighbor card To monitoring switch (eg. 10GbE) To monitoring switch (eg. 10GbE)

  10. ATCA-SRS Upgrade Schedule and cost • Current cost/blade: ~3k EUR (based on one full crate order, i.e. 14 blades) • Upgrade cost driven mainly by the FPGA cost • Variant B • Schedule ~ 12 weeks delivery for prototypes (Eicsys) • V7 mezzanine proto design by IFIN-HH (see backup) • Discussion: perhaps we may find a way to integrate the LAr AMC design • Variant A may take longer

  11. Backup

  12. Related developments at IFIN-HH • High Density Optical Mezzanine • Under definition at IFIN-HH • MiniPods • V7 (?) • SFP+ Mezzanine • advanced design at IFIN-HH/CERN • 8 x SFP+ • up to 25 Gbps (RX/TX)

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