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Trigger Status

Trigger Status. Cristiano Santoni Mauro Piccini (INFN – Sezione di Perugia). Firmware Status. The majority of the building blocks of the firmware has been developed. We are now running simulations to verify the correct behavior of the blocks. GPU Trigger. - Development - Simulation.

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Trigger Status

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  1. Trigger Status Cristiano Santoni Mauro Piccini (INFN – Sezione di Perugia)

  2. Firmware Status The majority of the building blocks of the firmware has been developed. We are now running simulations to verify the correct behavior of the blocks. GPU Trigger - Development - Simulation from Binning Logic Time Sorting - Development - Simulation - Development - Simulation 5ns Bin Generation Plane-based Sorting - Development - Simulation - Development - Simulation - Development - Simulation - Development - Simulation L0 Trigger Pairs Generation Pairs Correction Event Discovering Output Formatting

  3. Trigger algorithm The trigger algorithm presented during the meeting in Mainz has been developed in all its building blocks. The first and the last block showed in the previous slide, needed to adapt the input and the output to the rest of the firmware, will be developed as soon as possible. Currently the blocks already developed are simulated (using Modelsim) in order to verify that they correctly responds to every possible input data and to avoid unexpected input configuration. Some alternatives for the two missing blocks have been designed and there is the need of some information to choose between different possibilities

  4. Time sorting The current trigger algorithm is based on the assumption of sorted input data. To modify the algorithm in order to remove this assumption could increase the processing time and the resource utilization (both logic and memory utilization). Whereas the data are semi-sorted (at least within a single channel), the best choice is to use a sorting algorithm. In order to optimize the sorting algorithm it is desirable to know the maximum “delay” for an hit to arrive to the trigger logic. Anyway, on Internet there are a lot of articles that propose implementations on FPGA of generic sorting algorithms, therefore without any assumption on input data.

  5. Output Formatting The current trigger algorithm produces data such as number of hits per quadrant, number of total hits, average time of the hits. This data will be organized by a dedicated block into trigger primitives, according to a precise format. 1 – Multiplicity Histogram (Official) 0 3 32 36 40 44 48 52 56 60 63 Detector TimestampM1 M2 m3 M4 M5 M6 M7 M8 X –Time resolution 25ns/8 V –Maximum rate= 1 word/25ns 2 – Average finetime + Multiplicity 3 0 32 40 46 54 60 63 Detector TimestampF.T. 1 Mult 1 F.T. 2 Mult 2 CtrL V - Time resolution 100 ps X - Possible increase in the words rate

  6. Resource Utilization • Currently the resource utilization for the trigger algorithm is low: • Logic utilization 2 % • Combinational ALUTs 1,300 / 86,000 ( 2 % ) • Memory ALUTs 224 / 43,000 ( < 1 % ) • Dedicated logic registers 1,249 / 86,000 ( 1 % ) • Total block memory bits 10,752 / 4,303,872 ( < 1 % ) • We must consider that in this report is absent the logic for the sorting algorithm, however taking into account the property of data, the optimization of the sorting algorithm should limit the resource utilization. • Even considering the generic sorting algorithm, the resource utilization is not overly compromised, for example for this implementation we need about 5KB of memory ( < 1 %).

  7. To Do • Some blocks still need to be developed (input/output) • Most of the block need to be simulated • After the two previous steps are done, the trigger has to be integrated • in the TELL62 framework

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