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Asynchronous Multiplier – hw4. EE 577b – Fall 2001 Prof. Peter Beerel. split. asynchAdder8b 8-bit full adder behavior model. ByteGen. comp. Bit bucket. split. asynchAdder8 8-bit full adder from hw3. C A[0,7] B[0,7]. split. test bench. Adder test bench. 4x4 bit array multiplier.

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asynchronous multiplier hw4

Asynchronous Multiplier – hw4

EE 577b – Fall 2001

Prof. Peter Beerel

Marcos Ferretti

adder test bench

split

asynchAdder8b

8-bit full adder

behavior model

ByteGen

comp

Bit bucket

split

asynchAdder8

8-bit full adder

from hw3

C

A[0,7]

B[0,7]

split

test bench

Adder test bench

Marcos Ferretti

4x4 bit array multiplier
4x4 bit array multiplier

from J. M. Rabaey, Digital Integrated Circuits, Prentice Hall, NJ 1996

Marcos Ferretti

4x4 carry save multiplier
4x4 carry-save multiplier

from J. M. Rabaey, Digital Integrated Circuits, Prentice Hall, NJ 1996

Marcos Ferretti

multiplier test bench

asynchMult8b

8-bit multiplier

behavior model

ByteGen

comp

Bit bucket

split

asynchMult8

8-bit multiplier

implementation

A[0,7]

B[0,7]

split

test bench

Multiplier test bench

Marcos Ferretti