**Module 3Combinational and Sequential Logic Circuit** By: Cesar Mendoza

**Combinational logic:** • Combinational logic: When logic gates (such as AND, OR and NOT) are connected together to produce a specified output for certain specified combinations of input variables, with no storage involved • “is that logic in which all outputs are directly related to the current combination of values on its inputs”.

**The Exclusive-OR and Exclusive-NOR gates** • Exclusive-OR (XOR)

**XOR Logical Operation and Truth Table** • The logical operation of XOR is such that the output is high only when the two inputs are at opposite levels

**XOR Logical Function** • The two variables expression “X = AB” is called the Logical XOR Function

**The Exclusive-NOR (XNOR)**

**XNOR Logical Operation and Truth Table** • The logical operation of XNOR is such that when the two inputs are opposite the output is LOW.

**XNOR Logical Function** • The expression is called the Logical XNOR Function • Then the output of XNOR can be written as and it means: • If A and B both are High or both Low, then X is High. Otherwise X isLow

**XNOR Logical Function** • Then the output of XNOR can be written as • and it means: • If A and B both are High or both Low, then X is High. Otherwise X isLow

**QUESTION #1** • What is combinational logic Circuit? • Draw the combinational circuit for XOR gate. • What is the logical operation of XOR gate • Construct and complete 2 input Truth Table for XOR gate.

**QUESTION #2** • What is combinational logic Circuit? • Draw the combinational circuit for XNOR gate. • What is the logical operation of XNOR gate • Construct and complete 2 input Truth Table for XNOR gate.

**Example of Combinational Logic** • Central Heating Pump

**Truth Table for Central Heating Pump**

**Example of Combinational Logic** • Multiplexer

**Truth Table for Multiplexer**

**Sequential Logic** • A digital logic function made of basic logic gates (AND, OR, NOT, etc.) in which the output values depend not only on the values currently being presented to its inputs, but also on previous input values. • “is that logic in which the output depends on a sequence of its input values”.

**Latches and Flip-Flops**

**The NOR Gate S-R Latch** • Cross coupled NOR Gate Latch logic symbol S-R Latch logic Circuit

**0** 1 0 • initially assume that both inputs R and S and output Q are LOW • [i.e. R = S = 0 and Q = 0] 0 1 0

**0** 1 0 • Now G2 inputs are G = 0 and S = 0, therefore G2 output is = 1. • G1 inputs are Q = 1 and R = 0, therefore G1 output is Q = 0. 0 1 0

**0** 1 0 0->1 1 1 0 1-> 0 0 1 0->1 • Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2 output is = 0. • Now G1 inputs will change to = 0 and R = 0, therefore G1 output will change to Q = 1 the latch is in the Set state.

**0** 1 0 0->1 1 1-> 0 0 1->0 1 0 • Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2 output is = 0. • Now G1 inputs will change to = 0 and R = 0, therefore G1 output will change to Q = 1 the latch is in the Set state.

**0->1** 1 10 01 1->0 10 0->1 01 0 0 • Change S to HIGH G2 inputs become Q = 0 and S = 1, therefore G2 output is = 0. • Now G1 inputs will change to = 0 and R = 0, therefore G1 output will change to Q = 1 the latch is in the Set state.

**QUESTION #3** • What is sequential logic circuit? • What is the difference between latch and flip flop? • Complete the Truth Table for RS Latch • What does “No Change Means”? • What is “invalid Condition Means”?

**Flashback Lesson** • Distinctive Shape – Rectangular Shape Symbol

**Level Triggered Latches** • To have control over the Latch’s operation, a clock signal is applied to decide when a latch is enabled or disabled and when the output changes its state. The clock signal ensures that the device is triggered into operation at the right time and is denoted with C Clock Signal or EN Enable Signal • Level Triggered latch can be defined as “a logic device that changes its output state in response to a HIGH or LOW level of the clock”;

**Level triggered SR Latch**

**Level Triggered D-type Latch** • The D-type latch is basically a S-R latch with small circuit modification. This modification was introduced to ensure that the S and R inputs are never HIGH or LOW at the same time. So D-latch is used to eliminate the undesirable invalid state occurs in the S-R latch. • “The D-type latch is a Data-type circuit that can latch (store) a binary 1 or 0”.

**Level Triggered D-type Latch**

**Question #4** • What is “level triggered latch” means? • Draw the symbol of level triggered SR latch. • Draw the level triggered SR latch circuit. • Complete the truth table for level triggered SR latch.

**Flashback--- Question #1:** • Draw the distinctive symbol and the equivalent rectangular symbol of the following basic gates: • AND • OR • NOT • NAND • NOR

**Review Exercise:** • “is that logic in which all outputs are directly related to the current combination of values on its inputs”. • Combinational Logic • Sequential Logic • Common Logic • The logical operation of XOR is such that the output is high only when the two inputs are at opposite levels • OR Gate • XNOR Gate • XOR Gate • “is that logic in which the output depends on a sequence of its input values”. • Combinational Logic • Sequential Logic • Common Logic

**Review Exercise:** • It is a synchronous bistable device that can have its output changes state only on the clock edge. • Flip Flop • Latch • Level Trigger • Latch remains in previous state (store the previous output. • Latch • No Change • Reset • It is a bistable element that can have its output latched HIGH (Set) or LOW (Reset), hence the name S-R Latch. • Flip Flop • Latch • Level Trigger