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From analog to digital circuits. A phenomenological overview. Bogdan Roman. Outline. Insulators, conductors and semiconductors Semiconductor diodes: the p-n junction The Field Effect Transistor (FET): The Junction FET (JFET) The Metal Oxide Semiconductor FET (MOSFET) The MOS Inverter

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from analog to digital circuits

From analog to digital circuits

A phenomenological overview

Bogdan Roman

  • Insulators, conductors and semiconductors
  • Semiconductor diodes: the p-n junction
  • The Field Effect Transistor (FET):
    • The Junction FET (JFET)
    • The Metal Oxide Semiconductor FET (MOSFET)
  • The MOS Inverter
    • Resistive and same MOS type
    • Complementary MOS (CMOS) technology
  • Elementary gates
  • Flip-flops
  • Examples

Loosely based on the IA and 3B Engineering dept. courses

(Linear Circuits and Devices, Digital Circuits,Information Processing, Integrated Digital Electronics)

semiconductors intrinsic silicon
Semiconductors: Intrinsic silicon

At room temperature, the thermal energy kT ~ 1/40 eV is enough to break a few covalent bonds to produce free electrons. This also leaves holes(i.e. positive net charges left by the broken covalent bond).

Both electrons and holes contribute to current flow.

At low temperatures, silicon is an insulator since there is not enough thermal energy to break the covalent bonds.

the junction field effect transistor jfet
The Junction Field Effect Transistor (JFET)

- Proposed by Shockley in 1951

- First made by Teszner in 1958 in France

JFET Interactive (opens browser)

metal oxide semiconductor fet mosfet
Metal Oxide Semiconductor FET (MOSFET)
  • - First made in 1960 at Bell Laboratories in the USA by Atalla and Kahng.
  • Offers extremely high component density in integrated circuits.
  • - Very high input resistance, low noise, simpler fabrication than bipolar transistors.

MOSFET Interactive (opens browser)

the nmos inverter
The NMOS inverter

Resistive load:

NMOS load:

  • When input is low (0) then T1 is off, hence output goes high (1) (i.e. VDD)
  • When VIN = high (1) then T1 conducts (linear region) and brings the output low (0), depending on RL
  • High RL = low logic zero and low power consumption but large area on silicon and slow switching => compromise
  • T2 has the gate tied to its drain and is always on (and in saturation). Acts as a pseudo-resistor load.
  • Similar operation to the resistive load inverter
  • Smaller area on silicon (so easier to manufacture) and faster switching but has a lower high logic voltage (VDD – VT), and high power consumption when input high.
complementary mos cmos inverter
Complementary MOS (CMOS) inverter

In CMOS technology, the output is clamped to one of the power rails by a conductive (on) device, while the other device serves as a load of effectively infinite resistance (off). This leads to static properties that approximate those of the ideal inverter.

- The PMOS devices is slower (lower mobility of holes) so it has to be larger to compensate. It is also more complex to manufacture.

nor and nand gates
NOR and NAND gates

The 74HC02 IC has four 2-input NOR gates

The 74HC00 IC has four 2-input NAND gates


A crucial circuit, vital for implementing functions: