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KM3NeT CLBv2

KM3NeT CLBv2. Visual Status. IP/UDP Packet Buffer Stream Selector (IPMUX). 31 TDCs. Start Time Slice UTC & Offset counter since. Fifo. TDC0. Time Slice Start. RxPort 1. RxPacket Buffer 64KB. 31 PMTs. RxPort 2. Rx Stream Select. Fifo. TDC 30. Rx_mac2buf. Rx_buf2data. Flags.

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KM3NeT CLBv2

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  1. KM3NeT CLBv2

  2. Visual Status IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control S State Machine Management & Config. Pause Frame Fifo ADC Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf Management & Control Flags TxPort_m S S Nano Beacon M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

  3. Status Listing • Done: • LM32 + WB-Crossbar + DPRAM + UART • Soft-PLL FMC layout • WR without PCI-express • Currently: • Deterministic PHY => First shot White Rabbit in KC705 • Soft PLL (hardware + software). First goal: lock onto a 125 MHz xtal and phase shift under control of LM32 via UART • To do (in order of priority): • Endpoint (= MAC) <= Complex! • Mini-nic <= Complex! • Fabric redirector <= probably less complex • PPS generator <= relatively straightforward • 1-wire, SysCon <= easy?

  4. Planning (White Rabbit + IP-Mux) • Integration 1 month from now… Ouch! • Currently: • Soft PLL (hardware + software) => 2 month? • Endpoint (= MAC) <= Complex! => 1 month? • Mini-nic <= Complex => 1 month? • Fabric redirector <= probably less complex • PPS generator <= relatively straightforward • 1-wire, SysCon <= easy? • Connection Endpoint  IP-MUX => 2 weeks? • Estimation: ~4,5 Month (if we are lucky)! • Please also note: Peter is involved in another project the coming months!

  5. Planning Intergration • Integration of other objects • White Rabbit + IP-Mux • 2nd LM32 system • TDC’s / FIFOs / State Machine • Hydrophone • => Create complete design (hardware, software) + test environment (simulation)

  6. White Rabbit for Kintex7Slave Clock distribution xwr_core.vhd Entity: xwr_core Kc705_top.vhd Entity: kc705_top SoftPLL FMC wr_core.vhd Entity: wr_core wr_gtx_phy_kintex7.vhd Entity: wr_gtx_phy_kintex7 CDCM 61004 fpga_pll_ref_clk_123_p_i ????.vhd Entity: xwr_softpll_ng dac_dpll GTXE2_CHANNEL 62.5 MHz fpga_pll_ref_clk_123_n_i RXOUTCLK_OUT BUFG clk_ref_i(0) VCXO 25MHz DAC1 RXUSRCLK_IN clk_fb_i(0) rx_rbclk_o HPC FMC only! RXUSRCLK2_IN rx_rec_clk fpga_pll_ref_clk_101_p_i IBUFDS_GTE2 clk_gtx_i clk_dmtd_i gtx_dedicated_clk TXOUTCLK_OUT GTREFCLK0_IN BUFG clk_sys_i fpga_pll_ref_clk_101_n_i TXUSRCLK_IN SPEC = Spartan6 pin C11/D11 TXUSRCLK2_IN tx_out_clk_o CPLLRESET_IN rst_done_n xwr_endpoint.vhd Entity: xwr_endpoint clk_ref_i rst_i phy_ref_clk_i Gtp_bitslide.vhd Entity: gtp_bitslide phy_ref_clk_i clk_dmtd_i clk_125m_pllref_p_i IBUFGDS clk_sys_i clk_125m_pllref FPGA_CLK_P/N clk_125m_pllref_n_i Timing reference (125 MHz) clk_ref_i clk_dmtd_i SPEC = FPGA_CLK_P/N Spartan6 pin G9/F10 PLL_BASE Cmp_sys_clk_pll BUFG pllout_clk_sys clk_ref, phy_ref_clk = TXOUTCLK (62.5 MHz) Clk_sys = used for synchronizing reset signals => must run always! (62.5 MHz) Gc_extend_pulse ? Clk_i PLL25DAC_DIN PLL25DAC_SCLK PLL25DAC1_SYNC_N PLL25DAC2_SYNC_N dac_hpll HPC FMC only! VCXO 20MHz Clk_20m_vcxo_i CLK20_VCXO DAC2 PLL_BASE Cmp_dmtd_clk_pll BUFG pllout_clk_dmtd BUFG clk_dmtd (62.5x MHz)

  7. First shot KC705_top • Tried first shot for White Rabbit on Kintex7 • Solved issue with synchronous reset (reset switched off the clock ) • Only found this through simulating the design!! • KC705_top should do exactly the same as SPEC_top: • KC705_TOP hangs! • Why? • Sherlock Holmes • (Software/Hardware)

  8. Shore Station Broadcast brainstorm ReferenceClock Broadcast • Switch Routing Table (software?) needs to be adjusted. • PTP timestamps t1 for all DOMs are equal and reside in outgoing port (needs firmware- or software-change or both) • MAC Control-Level multicast MAC addresses; such as “pause frames” for flow control need to be handled correctly. Example: • “DOM-B” request “Pause” = Okay (request over point to point link), but… • “Shore station” request “Pause” may be problematic (request over broadcast link, all ports are stalled). Address single DOM? • Other surprises? Start PTP Tx Port-1 SFP Buffer Buffer Time Stamp t1 DOM A Buffer Buffer Port-2 SFP Optical Network Rx Time Stamp t4 t4 Stop1 DOM B j: DDMTD Port-3 SFP t4 Stop2 Time Stamp t4 Rx DOM C j: DDMTD Port-4 SFP t4 Stop3 Rx Time Stamp t4 DOM D j: DDMTD Port-5 SFP t4 Stop4 Time Stamp t4 Rx j: DDMTD Main Electrical Optical Cable Shore Station interface

  9. Shore Station BroadcastMAC Control Level • IEEE802.3 Clause 31 • For example “Pause frames” for flow control (IEEE802.3 Annex 31B) • MAC Destination Address • multicast 01-80-C2-00-00-01 or unicast? (see Annex31B 310.0.1) • MAC Source Address • Length Type • 88-08 for “this is a MAC Control Frame” • MAC Control Opcode • IEEE802.3 Annex31a => 00-01 for “pause” • MAC Control Parameter • Pause Quanta (1 Quanta = 512 bit times)

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