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Chapter Six

Chapter Six. Pipelining: How it works. Basic Idea: start with single cycle datapath. Each step of instruction mapped onto the datapath from left to right. Exceptions: update of the PC and writeback step (shown in color) send to left. Basic Idea: start with single cycle datapath.

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Chapter Six

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  1. Chapter Six Pipelining: How it works

  2. Basic Idea: start with single cycle datapath • Each step of instruction mapped onto the datapath from left to right. • Exceptions: update of the PC and writeback step (shown in color) send to left.

  3. Basic Idea: start with single cycle datapath • Use multiple cycles per instruction, but use the single cycle datapath • Data flowing from left to right do not affect current instruction. • Data flowing from right to left: • writeback step (shown in color) send to left. Can lead to data hazards • update of the PC. Can lead to control hazards. • Graphical presentation: pretend that each instruction has own datapath.

  4. Basic Idea: start with single cycle datapath • See next slide. • Execution of the instructions given previously. • Shades units according to use. • Each stage labeled by the physical resource used in that stage. • Breaks register file into two logical parts: • registers read during register fetch stage (ID) • registers written during write back stage (WB) • Draw the unshaded left half of register file using dashed lines in ID stage, unshaded right half in dashed lines in WB stage.

  5. Basic Idea: start with single cycle datapath

  6. Basic Idea: start with single cycle datapath • Do we need 3 datapaths? • Not if we store intermediate results in registers! • Each functional unit is used in only one of the 5 stages of an instruction. • Allows functional units to be used by different instructions in consecutive stages. • Must add registers wherever there is a line between stages. • See next slide. • All instructions advance during each clock cycle from one pipeline register to next. • Registers named for the two stages separated by that register.

  7. Basic Idea: start with single cycle datapath • the two stages separated by that register.

  8. Basic Idea: start with single cycle datapath • No register at end of write-back stage. • All instructions must update state in the machine, ie must change value in some storage area (register file, PC, memory). • Example: a load instruction places a value in the register file. • Later instructions use the register file. • Next slides show the active portions of the datapath highlighted as a load instruction goes through the 5 stages of pipelined execution. • Highlight right half of register or memory when read. • Highlight left half of register or memory when written.

  9. Stages: Instruction fetch. • Instruction read from memory using PC and placed in IF/ID register. • PC incremented by 4, written back to PC • also saved in IF/ID pipeline register in case needed later.

  10. Stages: Instruction fetch.

  11. Stages: instruction decode and register file read • IF/ID pipeline register supplies 16-bit immediate field • Extended to 32 bits • IF/ID pipeline register supplies the register numbers to read the two registers. • All 3 values stored in ID/EX pipeline register, along with incremented PC address.

  12. Stages: Instruction fetch.

  13. Stages: execute or address calculation • Reads contents of register 1 and the sign-extended immediate from ID/EX pipeline register and adds them using ALU. • Sum placed in EX/MEM pipeline register.

  14. Stages: execute or address calculation

  15. Stages: memory access • Data memory read using the address from the EX/MEM pipeline register. • Load data into the MEM/WB pipeline register.

  16. Stages: memory access

  17. Stages: Write back • Read data from MEM/WB pipeline register and write it into the register file.

  18. Stages: memory access

  19. Example: store word instruction fetch • Instruction read from memory using PC, placed in IF/ID register.

  20. Example: store word instruction fetch

  21. Example: sw instruction decode and reg file read • Instruction in IF/ID register supplies register numbers for 2 read registers and extends the sign of the 16-bit immediate. • These 3 32-bit values all stored in the ID/EX register. • Same as for lw

  22. Sw: instruction decode and register file read

  23. sw execute or address calculation • Reads contents of register 1 and the sign-extended immediate from ID/EX pipeline register and adds them using ALU. • Sum placed in EX/MEM pipeline register.

  24. sw execute or address calculation

  25. sw memory access • Data read into memory using the address from the EX/MEM pipeline register. • This address was calculated in stage 2 and stored in ID/EX register. • In stage 3 it was moved to the EX/MEM register

  26. Stages: memory access

  27. sw Write back • Nothing done for this instruction • Cannot accelerate following instructions because they’re already started. • Every instruction passes through every stage even if it doesn’t do anything.

  28. Stages: memory access

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