CPLD

Jul 16, 2014

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PLD bypass (Clk, Trig, Abort only). 3. Front-panel. CPLD. VME Backplane. NIM In. Enables and Mapping. 10. B-Sigs Out. 4. Push-Buttons. 3. Trigger Delay. GeogAddr. 5. Registers. VME Interface. NIM Out. Address Bus. 10. 32. Repetitive Trigger Generate. Data Bus. 16.

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CPLD

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PLD bypass (Clk, Trig, Abort only) 3 Front-panel CPLD VME Backplane NIM In Enables and Mapping 10 B-Sigs Out 4 Push-Buttons 3 Trigger Delay GeogAddr 5 Registers VME Interface NIM Out Address Bus 10 32 Repetitive Trigger Generate Data Bus 16 L-Sigs Out 40 10 VME Control ~30 V-Sigs Generate 4x Hex Switch BaseAddr 16 Delay Unit 1 Delay1Set 6 Trigger Abort Logic 12.5MHz IntClk Generate Delay Unit 2 50 MHz Clock Delay2Set LocalClk 6 Trigger Board Block Diagram