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Xilinx M1.5 Software CPLD Fitter

Xilinx M1.5 Software CPLD Fitter. Agenda. Design Manager JTAG Programmer Advance Options PT/Input Collapse Limit Report Options and Format Design Example SDRAM Controller Lab. Design/Project Manager. Design/Project Manager M1.5. Options. User constraint file Implementation options

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Xilinx M1.5 Software CPLD Fitter

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  1. Xilinx M1.5 Software CPLD Fitter

  2. Agenda • Design Manager • JTAG Programmer • Advance Options • PT/Input Collapse Limit • Report Options and Format • Design Example SDRAM Controller • Lab

  3. Design/Project Manager

  4. Design/Project Manager M1.5

  5. Options • User constraint file • Implementation options • Simulation options • Target options • Post Layout Timing Report moved to Timing Tab

  6. Implementation: Standard Options • Allow for quick selection • Optimize for: • speed • density

  7. Simulation: Output Options • Select output file format for post-fit timing simulation

  8. Tabs • Basic • Advanced • Timing Reports • Programming • Interface

  9. Basic

  10. Basic • Utilize global resources by type • enables automatic assignment of clock, output enable and set/reset input signals or pin feedback of I/O signals to global nets • individual signals can be assigned to global nets with attributes • Timing Constraints • causes fitter to optimize constrained paths for priority timing paths (use timing constraints sparingly) • off yields better density

  11. Basic • Design Location Constraints • let software assign pins on first pass • enable for Pinlocking on subsequent passes • Create Programmable Grounds • allows hardware to tie unused pins to ground (suggested)

  12. Basic • Macrocell power setting • set to low or timing driven for most cases • Output Slew Rate • set to low or timing driven for most cases • high slew rate will tend to cause design issues, without much gain in performance

  13. Advanced Tab

  14. Advanced Tab • Timing Optimization • General timing optimization tends to speed up slowest paths in design • Turning this option off Optimizes for Density and minimizes product terms • Multi-level Logic Optimization • Optimization algorithm which provides for more efficient logic mapping • T-type Register Synthesis • Enables conversion of D-type registers to T-type (suggested)

  15. Advanced Tab • Use Advanced Fitting • Different partitioning algorithm places stronger emphasis on mapping functions that share inputs into the same FB • Use if designs become FB input limited • Use Local Macrocell Feedback (not available on 9500XL) • Logic is mapped into same FB so it can use local feedback rather than Standard Feedback • Since Wire-ANDing is done in the FastConnect I, Logic cannot require Wire-ANDing to make the design fit • Wire-ANDing not available on 9500XL FastConnect II

  16. Advanced Tab • Pterm Collapse Limit • limits how many terms can be used by a function • max= 90 (# pterms per FB) • Input Limit • limits how many inputs function can use • max= 36 (# inputs per FB) for XC9500 • max=54 for XC9500XL

  17. Collapsing Product Term Limit Product Term Allocator D/T Macrocell Product Terms Borrowed Product Terms

  18. Timing Reports • Enables option for level of detail on timing report

  19. Programming • User code selection • TMV file option for Intest via boundry scan

  20. Interface • Interface options allow for multiple macro sets without having to change system variables

  21. Program XC9500/XL Configure/verify FPGA’s (XC4000, XC5200, Spartan) Exercise devices through Boundry scan/JTAG port clamp verify erase functional test blankcheck readback Jedec query device id query usercode query checksum JTAG Programmer

  22. JTAG Programmer

  23. Design Example • Sync DRAM controller • Project included on lab disk as sdram1 • File included on lab disk as sdramctl.vhd • Report and timing files included • Netlist file included

  24. Fitting Report -Resources

  25. Fitting Report- Resources (cont)

  26. Fitting Report- FB Global

  27. Fitting Report- PT by FB

  28. Fitting Report - FB Map

  29. Fitting Report - Equations

  30. Dot Extensions Definition .CLKF Register clock .SETF Register asynchronous set .RSTF Register asynchronous reset .TRST Pin output enable .INTRST Macrocell output enable .PIN Feedback from I/O pin .LFBK Local feedback from macrocell in same function block .PRLD Register preload value Logic Operators / * + :+: = := NOT AND OR Exclusive OR Combinatorial assignment Registered assignment Equation Syntax

  31. Timing Report (Summary)

  32. Timing Report (Summary)

  33. Timing Report (Detailed)

  34. Timing Analyzer • Button to invoke • Buttons for constraint verification • paths constrained • paths not met • paths not constrained • Button for “Advanced” Timing Analysis • same as summary report

  35. Conclusion • Xilinx CPLD implementation tools give push-button ease-of-use or detailed control over fitting • Fitting and Timing Reports provide detailed review of settings and their effects

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